OpenCore  1.0.4
OpenCore Bootloader
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PciInfoDump.c
Go to the documentation of this file.
1
16#include <Uefi.h>
17
18#include <IndustryStandard/Pci.h>
19
20#include <Protocol/PciIo.h>
21
22#include <Library/BaseLib.h>
23#include <Library/BaseMemoryLib.h>
24#include <Library/DebugLib.h>
25#include <Library/DevicePathLib.h>
26#include <Library/IoLib.h>
27#include <Library/MemoryAllocationLib.h>
29#include <Library/PrintLib.h>
30#include <Library/UefiBootServicesTableLib.h>
31
32typedef struct PCI_CLASS_ENTRY_TAG {
33 UINT8 Code; // Class, subclass or interface code
34 CONST CHAR8 *DescText; // Description string
35 CONST struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or interface if any
37
38//
39// PCI subclasses.
40//
41
42//
43// Pre-classcode subclass.
44//
46 {
47 PCI_CLASS_OLD_OTHER,
48 "Other device",
49 NULL
50 },
51 {
52 PCI_CLASS_OLD_VGA,
53 "VGA-compatible device",
54 NULL
55 },
56 {
57 0x00,
58 NULL,
59 NULL
60 }
61};
62
63//
64// Mass storage subclasses.
65//
66
67// SCSI controller interfaces.
69 {
70 0x00,
71 "SCSI controller",
72 NULL
73 },
74 {
75 0x11,
76 "SCSI storage device SOP using PQI",
77 NULL
78 },
79 {
80 0x12,
81 "SCSI controller SOP using PQI",
82 NULL
83 },
84 {
85 0x13,
86 "SCSI storage device and controller SOP using PQI",
87 NULL
88 },
89 {
90 0x21,
91 "SCSI storage device SOP using NVMe",
92 NULL
93 },
94 {
95 0x00,
96 NULL,
97 NULL
98 }
99};
100
101// ATA controller interfaces.
103 {
104 0x20,
105 "ATA controller with single stepping ADMA interface",
106 NULL
107 },
108 {
109 0x30,
110 "ATA controller with continous ADMA interface",
111 NULL
112 },
113 {
114 0x00,
115 NULL,
116 NULL
117 }
118};
119
120// Serial ATA controller interfaces.
122 {
123 0x00,
124 "Serial ATA controller",
125 NULL
126 },
127 {
128 0x01,
129 "Serial ATA controller using AHCI",
130 NULL
131 },
132 {
133 0x02,
134 "Serial Storage Bus interface",
135 NULL
136 },
137 {
138 0x00,
139 NULL,
140 NULL
141 }
142};
143
144// Non-volatile memory subsystem interfaces.
146 {
147 0x00,
148 "Non-volatile memory subsystem",
149 NULL
150 },
151 {
152 0x01,
153 "Non-volatile memory subsystem using NVMHCI",
154 NULL
155 },
156 {
157 0x02,
158 "NVM Express I/O controller",
159 NULL
160 },
161 {
162 0x03,
163 "NVM Express administrative controller",
164 NULL
165 },
166 {
167 0x00,
168 NULL,
169 NULL
170 }
171};
172
173// Universal Flash Storage controller interfaces.
175 {
176 0x00,
177 "Universal Flash Storage controller",
178 NULL
179 },
180 {
181 0x01,
182 "Universal Flash Storage controller using UFSHCI",
183 NULL
184 },
185 {
186 0x00,
187 NULL,
188 NULL
189 }
190};
191
193 {
194 PCI_CLASS_MASS_STORAGE_SCSI,
195 "SCSI controller",
197 },
198 {
199 PCI_CLASS_MASS_STORAGE_IDE,
200 "IDE controller",
201 NULL
202 },
203 {
204 PCI_CLASS_MASS_STORAGE_FLOPPY,
205 "Floppy controller",
206 NULL
207 },
208 {
209 PCI_CLASS_MASS_STORAGE_IPI,
210 "IPI bus controller",
211 NULL
212 },
213 {
214 PCI_CLASS_MASS_STORAGE_RAID,
215 "RAID controller",
216 NULL
217 },
218 {
219 0x05,
220 "ATA controller",
222 },
223 {
224 0x06,
225 "Serial ATA controller",
227 },
228 {
229 0x07,
230 "Serial Attached SCSI controller",
231 NULL
232 },
233 {
234 0x08,
235 "Non-volatile memory subsystem",
237 },
238 {
239 0x09,
240 "Universal Flash Storage controller",
242 },
243 {
244 PCI_CLASS_MASS_STORAGE_OTHER,
245 "Other mass storage controller",
246 NULL
247 },
248 {
249 0x00,
250 NULL,
251 NULL
252 }
253};
254
255//
256// Network controller subclasses.
257//
259 {
260 PCI_CLASS_NETWORK_ETHERNET,
261 "Ethernet controller",
262 NULL
263 },
264 {
265 PCI_CLASS_NETWORK_TOKENRING,
266 "Token Ring controller",
267 NULL
268 },
269 {
270 PCI_CLASS_NETWORK_FDDI,
271 "FDDI controller",
272 NULL
273 },
274 {
275 PCI_CLASS_NETWORK_ATM,
276 "ATM controller",
277 NULL
278 },
279 {
280 PCI_CLASS_NETWORK_ISDN,
281 "ISDN controller",
282 NULL
283 },
284 {
285 0x05,
286 "WorldFip controller",
287 NULL
288 },
289 {
290 0x06,
291 "PCMIG 2.14 Multi Computing",
292 NULL
293 },
294 {
295 0x07,
296 "InfiniBand controller",
297 NULL
298 },
299 {
300 0x08,
301 "Host fabric controller",
302 NULL
303 },
304 {
305 PCI_CLASS_NETWORK_OTHER,
306 "Other network controller",
307 NULL
308 },
309 {
310 0x00,
311 NULL,
312 NULL
313 }
314};
315
316//
317// Display controller subclasses.
318//
319
320// VGA controller interfaces.
322 {
323 PCI_IF_VGA_VGA,
324 "VGA-compatible controller",
325 NULL
326 },
327 {
328 PCI_IF_VGA_8514,
329 "8514-compatible controller",
330 NULL
331 },
332 {
333 0x00,
334 NULL,
335 NULL
336 }
337};
338
340 {
341 PCI_CLASS_DISPLAY_VGA,
342 "VGA controller",
344 },
345 {
346 PCI_CLASS_DISPLAY_XGA,
347 "XGA controller",
348 NULL
349 },
350 {
351 PCI_CLASS_DISPLAY_3D,
352 "3D controller",
353 NULL
354 },
355 {
356 PCI_CLASS_DISPLAY_OTHER,
357 "Other display controller",
358 NULL
359 },
360 {
361 0x00,
362 NULL,
363 NULL
364 }
365};
366
367//
368// Multimedia controller subclasses.
369//
371 {
372 PCI_CLASS_MEDIA_VIDEO,
373 "Video device",
374 NULL
375 },
376 {
377 PCI_CLASS_MEDIA_AUDIO,
378 "Audio device",
379 NULL
380 },
381 {
382 PCI_CLASS_MEDIA_TELEPHONE,
383 "Telephony device",
384 NULL
385 },
386 {
387 0x03,
388 "High definition audio device",
389 NULL
390 },
391 {
392 PCI_CLASS_MEDIA_OTHER,
393 "Other multimedia device",
394 NULL
395 },
396 {
397 0x00,
398 NULL,
399 NULL
400 }
401};
402
403//
404// Memory controller subclasses.
405//
407 {
408 PCI_CLASS_MEMORY_RAM,
409 "RAM controller",
410 NULL
411 },
412 {
413 PCI_CLASS_MEMORY_FLASH,
414 "Flash memory controller",
415 NULL
416 },
417 {
418 PCI_CLASS_MEMORY_OTHER,
419 "Other memory controller",
420 NULL
421 },
422 {
423 0x00,
424 NULL,
425 NULL
426 }
427};
428
429//
430// Bridge subclasses.
431//
433 {
434 PCI_CLASS_BRIDGE_HOST,
435 "Host bridge",
436 NULL
437 },
438 {
439 PCI_CLASS_BRIDGE_ISA,
440 "ISA bridge",
441 NULL
442 },
443 {
444 PCI_CLASS_BRIDGE_EISA,
445 "EISA bridge",
446 NULL
447 },
448 {
449 PCI_CLASS_BRIDGE_MCA,
450 "MCA bridge",
451 NULL
452 },
453 {
454 PCI_CLASS_BRIDGE_P2P,
455 "PCI-to-PCI bridge",
456 NULL
457 },
458 {
459 PCI_CLASS_BRIDGE_PCMCIA,
460 "PCMCIA bridge",
461 NULL
462 },
463 {
464 PCI_CLASS_BRIDGE_CARDBUS,
465 "CardBus bridge",
466 NULL
467 },
468 {
469 PCI_CLASS_BRIDGE_RACEWAY,
470 "RACEway bridge",
471 NULL
472 },
473 {
474 0x09,
475 "Semi-transparent PCI-to-PCI bridge",
476 NULL
477 },
478 {
479 0x0A,
480 "InfiniBand-to-PCI host bridge",
481 NULL
482 },
483 {
484 0x0B,
485 "Advanced Switching to PCI host bridge",
486 NULL
487 },
488 {
489 PCI_CLASS_BRIDGE_OTHER,
490 "Other bridge device",
491 NULL
492 },
493 {
494 0x00,
495 NULL,
496 NULL
497 }
498};
499
500//
501// Simple communication controller subclasses.
502//
503
504// Serial controller interfaces.
506 {
507 PCI_IF_GENERIC_XT,
508 "Generic XT-compatible serial controller",
509 NULL
510 },
511 {
512 PCI_IF_16450,
513 "16450-compatible serial controller",
514 NULL
515 },
516 {
517 PCI_IF_16550,
518 "16550-compatible serial controller",
519 NULL
520 },
521 {
522 PCI_IF_16650,
523 "16650-compatible serial controller",
524 NULL
525 },
526 {
527 PCI_IF_16750,
528 "16750-compatible serial controller",
529 NULL
530 },
531 {
532 PCI_IF_16850,
533 "16850-compatible serial controller",
534 NULL
535 },
536 {
537 PCI_IF_16950,
538 "16950-compatible serial controller",
539 NULL
540 },
541 {
542 0x00,
543 NULL,
544 NULL
545 }
546};
547
548// Parallel controller interfaces.
550 {
551 PCI_IF_PARALLEL_PORT,
552 "Parallel port",
553 NULL
554 },
555 {
556 PCI_IF_BI_DIR_PARALLEL_PORT,
557 "Bi-directional parallel port",
558 NULL
559 },
560 {
561 PCI_IF_ECP_PARALLEL_PORT,
562 "ECP parallel port",
563 NULL
564 },
565 {
566 PCI_IF_1284_CONTROLLER,
567 "IEEE1284 controller",
568 NULL
569 },
570 {
571 PCI_IF_1284_DEVICE,
572 "IEEE1284 device",
573 NULL
574 },
575 {
576 0x00,
577 NULL,
578 NULL
579 }
580};
581
582// Modem interfaces.
584 {
585 PCI_IF_GENERIC_MODEM,
586 "Generic modem",
587 NULL
588 },
589 {
590 PCI_IF_16450_MODEM,
591 "Hayes compatible modem, 16450-compatible interface",
592 NULL
593 },
594 {
595 PCI_IF_16550_MODEM,
596 "Hayes compatible modem, 16550-compatible interface",
597 NULL
598 },
599 {
600 PCI_IF_16650_MODEM,
601 "Hayes compatible modem, 16650-compatible interface",
602 NULL
603 },
604 {
605 PCI_IF_16750_MODEM,
606 "Hayes compatible modem, 16750-compatible interface",
607 NULL
608 },
609 {
610 0x00,
611 NULL,
612 NULL
613 }
614};
615
617 {
618 PCI_SUBCLASS_SERIAL,
619 "Serial controller",
621 },
622 {
623 PCI_SUBCLASS_PARALLEL,
624 "Parallel controller",
626 },
627 {
628 PCI_SUBCLASS_MULTIPORT_SERIAL,
629 "Multiport serial controller",
630 NULL
631 },
632 {
633 PCI_SUBCLASS_MODEM,
634 "Modem",
636 },
637 {
638 0x04,
639 "GPIB (IEEE448.1/2) controller",
640 NULL
641 },
642 {
643 0x05,
644 "Smart Card",
645 NULL
646 },
647 {
648 PCI_SUBCLASS_SCC_OTHER,
649 "Other communications device",
650 NULL
651 },
652 {
653 0x00,
654 NULL,
655 NULL
656 }
657};
658
659//
660// System peripheral subclasses.
661//
662
663// Interrupt controller interfaces.
665 {
666 PCI_IF_8259_PIC,
667 "Generic 8259 programmable interrupt controller",
668 NULL
669 },
670 {
671 PCI_IF_ISA_PIC,
672 "ISA programmable interrupt controller",
673 NULL
674 },
675 {
676 PCI_IF_EISA_PIC,
677 "EISA programmable interrupt controller",
678 NULL
679 },
680 {
681 PCI_IF_APIC_CONTROLLER,
682 "I/O APIC interrupt controller",
683 NULL
684 },
685 {
686 PCI_IF_APIC_CONTROLLER2,
687 "I/O x2 APIC interrupt controller",
688 NULL
689 },
690 {
691 0x00,
692 NULL,
693 NULL
694 }
695};
696
697// DMA controller interfaces.
699 {
700 PCI_IF_8237_DMA,
701 "Generic 8237 DMA controller",
702 NULL
703 },
704 {
705 PCI_IF_ISA_DMA,
706 "ISA DMA controller",
707 NULL
708 },
709 {
710 PCI_IF_EISA_DMA,
711 "EISA DMA controller",
712 NULL
713 },
714 {
715 0x00,
716 NULL,
717 NULL
718 }
719};
720
721// Timer interfaces.
723 {
724 PCI_IF_8254_TIMER,
725 "Generic 8254 system timer",
726 NULL
727 },
728 {
729 PCI_IF_ISA_TIMER,
730 "ISA system timer",
731 NULL
732 },
733 {
734 PCI_IF_EISA_TIMER,
735 "EISA system timer",
736 NULL
737 },
738 {
739 0x04,
740 "High Performance Event Timer",
741 NULL
742 },
743 {
744 0x00,
745 NULL,
746 NULL
747 }
748};
749
750// RTC interfaces.
752 {
753 PCI_IF_GENERIC_RTC,
754 "Generic RTC controller",
755 NULL
756 },
757 {
758 PCI_IF_ISA_RTC,
759 "ISA RTC controller",
760 NULL
761 },
762 {
763 0x00,
764 NULL,
765 NULL
766 }
767};
768
770 {
771 PCI_SUBCLASS_PIC,
772 "Programmable interrupt controller",
774 },
775 {
776 PCI_SUBCLASS_DMA,
777 "DMA controller",
779 },
780 {
781 PCI_SUBCLASS_TIMER,
782 "System timer",
784 },
785 {
786 PCI_SUBCLASS_RTC,
787 "RTC controller",
789 },
790 {
791 PCI_SUBCLASS_PNP_CONTROLLER,
792 "Generic PCI Hot-Plug controller",
793 NULL
794 },
795 {
796 0x05,
797 "SD Host controller",
798 NULL
799 },
800 {
801 0x06,
802 "IOMMU",
803 NULL
804 },
805 {
806 0x07,
807 "Root Complex Event Collector",
808 NULL
809 },
810 {
811 PCI_SUBCLASS_PERIPHERAL_OTHER,
812 "Other system peripheral",
813 NULL
814 },
815 {
816 0x00,
817 NULL,
818 NULL
819 }
820};
821
822//
823// Input device subclasses.
824//
826 {
827 PCI_SUBCLASS_KEYBOARD,
828 "Keyboard controller",
829 NULL
830 },
831 {
832 PCI_SUBCLASS_PEN,
833 "Pen controller",
834 NULL
835 },
836 {
837 PCI_SUBCLASS_MOUSE_CONTROLLER,
838 "Mouse controller",
839 NULL
840 },
841 {
842 PCI_SUBCLASS_SCAN_CONTROLLER,
843 "Scanner controller",
844 NULL
845 },
846 {
847 PCI_SUBCLASS_GAMEPORT,
848 "Gameport controller",
849 NULL
850 },
851 {
852 PCI_SUBCLASS_INPUT_OTHER,
853 "Other input controller",
854 NULL
855 },
856 {
857 0x00,
858 NULL,
859 NULL
860 }
861};
862
863//
864// Docking station subclasses.
865//
867 {
868 PCI_SUBCLASS_DOCKING_GENERIC,
869 "Generic docking station",
870 NULL
871 },
872 {
873 PCI_SUBCLASS_DOCKING_OTHER,
874 "Other docking station",
875 NULL
876 },
877 {
878 0x00,
879 NULL,
880 NULL
881 }
882};
883
884//
885// Processor subclasses.
886//
888 {
889 PCI_SUBCLASS_PROC_386,
890 "386 processor",
891 NULL
892 },
893 {
894 PCI_SUBCLASS_PROC_486,
895 "486 processor",
896 NULL
897 },
898 {
899 PCI_SUBCLASS_PROC_PENTIUM,
900 "Pentium processor",
901 NULL
902 },
903 {
904 PCI_SUBCLASS_PROC_ALPHA,
905 "Alpha processor",
906 NULL
907 },
908 {
909 PCI_SUBCLASS_PROC_POWERPC,
910 "PowerPC processor",
911 NULL
912 },
913 {
914 PCI_SUBCLASS_PROC_MIPS,
915 "MIPS processor",
916 NULL
917 },
918 {
919 PCI_SUBCLASS_PROC_CO_PORC,
920 "Co-processor",
921 NULL
922 },
923 {
924 0x80,
925 "Other processor",
926 NULL
927 },
928 {
929 0x00,
930 NULL,
931 NULL
932 }
933};
934
935//
936// Serial bus controller subclasses.
937//
938
939// FireWire controller interfaces
941 {
942 PCI_IF_1394,
943 "IEEE 1394 FireWire controller",
944 NULL
945 },
946 {
947 PCI_IF_1394_OPEN_HCI,
948 "IEEE 1394 OHCI controller",
949 NULL
950 },
951 {
952 0x00,
953 NULL,
954 NULL
955 }
956};
957
958// USB controller interfaces
960 {
961 PCI_IF_UHCI,
962 "Universal Serial Bus UHCI controller",
963 NULL
964 },
965 {
966 PCI_IF_OHCI,
967 "Universal Serial Bus OHCI controller",
968 NULL
969 },
970 {
971 0x20,
972 "Universal Serial Bus EHCI controller",
973 NULL
974 },
975 {
976 0x30,
977 "Universal Serial Bus xHCI controller",
978 NULL
979 },
980 {
981 0x40,
982 "USB4 Host Interface controller",
983 NULL
984 },
985 {
986 PCI_IF_USB_OTHER,
987 "Other Universal Serial Bus controller",
988 NULL
989 },
990 {
991 PCI_IF_USB_DEVICE,
992 "Universal Serial Bus device",
993 NULL
994 },
995 {
996 0x00,
997 NULL,
998 NULL
999 }
1000};
1001
1003 {
1004 PCI_CLASS_SERIAL_FIREWIRE,
1005 "FireWire controller",
1007 },
1008 {
1009 PCI_CLASS_SERIAL_ACCESS_BUS,
1010 "ACCESS.bus",
1011 NULL
1012 },
1013 {
1014 PCI_CLASS_SERIAL_SSA,
1015 "SSA",
1016 NULL
1017 },
1018 {
1019 PCI_CLASS_SERIAL_USB,
1020 "Universal Serial Bus controller",
1022 },
1023 {
1024 PCI_CLASS_SERIAL_FIBRECHANNEL,
1025 "Fibre Channel controller",
1026 NULL
1027 },
1028 {
1029 PCI_CLASS_SERIAL_SMB,
1030 "SMBus controller",
1031 NULL
1032 },
1033 {
1034 0x06,
1035 "InfiniBand controller",
1036 NULL
1037 },
1038 {
1039 0x07,
1040 "IPMI controller",
1041 NULL
1042 },
1043 {
1044 0x08,
1045 "SERCOS Interface Standard controller",
1046 NULL
1047 },
1048 {
1049 0x09,
1050 "CANbus controller",
1051 NULL
1052 },
1053 {
1054 0x09,
1055 "MIPI I3C Host Controller",
1056 NULL
1057 },
1058 {
1059 0x80,
1060 "Other serial bus controller",
1061 NULL
1062 },
1063 {
1064 0x00,
1065 NULL,
1066 NULL
1067 }
1068};
1069
1070//
1071// Wireless subclasses.
1072//
1074 {
1075 PCI_SUBCLASS_IRDA,
1076 "irDA-compatible controller",
1077 NULL
1078 },
1079 {
1080 PCI_SUBCLASS_IR,
1081 "Consumer IR controller",
1082 NULL
1083 },
1084 {
1085 PCI_SUBCLASS_RF,
1086 "RF controller",
1087 NULL
1088 },
1089 {
1090 0x11,
1091 "Bluetooth controller",
1092 NULL
1093 },
1094 {
1095 0x12,
1096 "Broadband controller",
1097 NULL
1098 },
1099 {
1100 0x20,
1101 "Ethernet 802.11a controller",
1102 NULL
1103 },
1104 {
1105 0x21,
1106 "Ethernet 802.11b controller",
1107 NULL
1108 },
1109 {
1110 0x40,
1111 "Cellular controller",
1112 NULL
1113 },
1114 {
1115 0x41,
1116 "Cellular controller plus Ethernet 802.11",
1117 NULL
1118 },
1119 {
1120 PCI_SUBCLASS_WIRELESS_OTHER,
1121 "Other wireless controller",
1122 NULL
1123 },
1124 {
1125 0x00,
1126 NULL,
1127 NULL
1128 }
1129};
1130
1131//
1132// Satellite communication subclasses.
1133//
1135 {
1136 PCI_SUBCLASS_TV,
1137 "Satellite TV controller",
1138 NULL
1139 },
1140 {
1141 PCI_SUBCLASS_AUDIO,
1142 "Satellite audio controller",
1143 NULL
1144 },
1145 {
1146 PCI_SUBCLASS_VOICE,
1147 "Satellite voice controller",
1148 NULL
1149 },
1150 {
1151 PCI_SUBCLASS_DATA,
1152 "Satellite data controller",
1153 NULL
1154 },
1155 {
1156 0x80,
1157 "Other satellite controller",
1158 NULL
1159 },
1160 {
1161 0x00,
1162 NULL,
1163 NULL
1164 }
1165};
1166
1167//
1168// Encryption/decryption subclasses.
1169//
1171 {
1172 PCI_SUBCLASS_NET_COMPUT,
1173 "Network and computing encryption and decryption controller",
1174 NULL
1175 },
1176 {
1177 PCI_SUBCLASS_ENTERTAINMENT,
1178 "Entertainment encryption and decryption controller",
1179 NULL
1180 },
1181 {
1182 PCI_SUBCLASS_SECURITY_OTHER,
1183 "Other encryption and decryption controller",
1184 NULL
1185 },
1186 {
1187 0x00,
1188 NULL,
1189 NULL
1190 }
1191};
1192
1193//
1194// Data acquisition and signal processing subclasses.
1195//
1197 {
1198 PCI_SUBCLASS_DPIO,
1199 "DPIO module",
1200 NULL
1201 },
1202 {
1203 0x01,
1204 "Performance counters",
1205 NULL
1206 },
1207 {
1208 0x10,
1209 "Communications synchronization plus time and frequency test/measurement",
1210 NULL
1211 },
1212 {
1213 0x20,
1214 "Management card",
1215 NULL
1216 },
1217 {
1218 PCI_SUBCLASS_DPIO_OTHER,
1219 "Other data acquisition/signal processing controller",
1220 NULL
1221 },
1222 {
1223 0x00,
1224 NULL,
1225 NULL
1226 }
1227};
1228
1229//
1230// PCI classes.
1231//
1233 {
1234 PCI_CLASS_OLD,
1235 "Legacy PCI class",
1237 },
1238 {
1239 PCI_CLASS_MASS_STORAGE,
1240 "Mass storage controller",
1242 },
1243 {
1244 PCI_CLASS_NETWORK,
1245 "Network controller",
1247 },
1248 {
1249 PCI_CLASS_DISPLAY,
1250 "Display controller",
1252 },
1253 {
1254 PCI_CLASS_MEDIA,
1255 "Multimedia controller",
1257 },
1258 {
1259 PCI_CLASS_MEMORY_CONTROLLER,
1260 "Memory controller",
1262 },
1263 {
1264 PCI_CLASS_BRIDGE,
1265 "Bridge device",
1267 },
1268 {
1269 PCI_CLASS_SCC,
1270 "Simple communications controller",
1272 },
1273 {
1274 PCI_CLASS_SYSTEM_PERIPHERAL,
1275 "Base system peripheral",
1277 },
1278 {
1279 PCI_CLASS_INPUT_DEVICE,
1280 "Input device",
1282 },
1283 {
1284 PCI_CLASS_DOCKING_STATION,
1285 "Docking station",
1287 },
1288 {
1289 PCI_CLASS_PROCESSOR,
1290 "Processor",
1292 },
1293 {
1294 PCI_CLASS_SERIAL,
1295 "Serial bus controller",
1297 },
1298 {
1299 PCI_CLASS_WIRELESS,
1300 "Wireless controller",
1302 },
1303 {
1304 PCI_CLASS_INTELLIGENT_IO,
1305 "Intelligent I/O controller",
1306 NULL
1307 },
1308 {
1309 PCI_CLASS_SATELLITE,
1310 "Satellite communication controller",
1312 },
1313 {
1314 PCI_SECURITY_CONTROLLER,
1315 "Encryption/decryption controller",
1317 },
1318 {
1319 PCI_CLASS_DPIO,
1320 "Data acquisition and signal processing controller",
1322 },
1323 {
1324 0x12,
1325 "Processing accelerator",
1326 NULL
1327 },
1328 {
1329 0x13,
1330 "Non-essential instrumentation function"
1331 }
1332};
1333
1334STATIC
1335VOID
1337 IN UINT8 BaseClass,
1338 IN UINT8 SubClass,
1339 IN UINT8 Interface,
1340 OUT CONST CHAR8 **TextBaseClass,
1341 OUT CONST CHAR8 **TextSubClass
1342 )
1343{
1344 UINTN Index;
1345 CONST PCI_CLASS_ENTRY *BaseClassEntry;
1346 CONST PCI_CLASS_ENTRY *SubClassEntry;
1347 CONST PCI_CLASS_ENTRY *InterfaceEntry;
1348
1349 //
1350 // Get base class.
1351 //
1352 BaseClassEntry = NULL;
1353 for (Index = 0; Index < ARRAY_SIZE (mPciClasses); Index++) {
1354 if (mPciClasses[Index].Code == BaseClass) {
1355 BaseClassEntry = &mPciClasses[Index];
1356 }
1357 }
1358
1359 if (BaseClassEntry == NULL) {
1360 *TextBaseClass = "Unknown class";
1361 *TextSubClass = NULL;
1362 return;
1363 }
1364
1365 *TextBaseClass = BaseClassEntry->DescText;
1366
1367 //
1368 // Get subclass if present.
1369 //
1370 if (BaseClassEntry->LowerLevelClass == NULL) {
1371 *TextSubClass = NULL;
1372 return;
1373 }
1374
1375 Index = 0;
1376 SubClassEntry = NULL;
1377 while (BaseClassEntry->LowerLevelClass[Index].DescText != NULL) {
1378 if (BaseClassEntry->LowerLevelClass[Index].Code == SubClass) {
1379 SubClassEntry = &BaseClassEntry->LowerLevelClass[Index];
1380 break;
1381 }
1382
1383 Index++;
1384 }
1385
1386 //
1387 // Use other subclass if subclass not found.
1388 //
1389 if (SubClassEntry == NULL) {
1390 Index = 0;
1391 while (BaseClassEntry->LowerLevelClass[Index].DescText != NULL) {
1392 if (BaseClassEntry->LowerLevelClass[Index].Code == SubClass) {
1393 SubClassEntry = &BaseClassEntry->LowerLevelClass[Index];
1394 break;
1395 }
1396
1397 Index++;
1398 }
1399 }
1400
1401 if (SubClassEntry == NULL) {
1402 *TextSubClass = NULL;
1403 return;
1404 }
1405
1406 //
1407 // Get interface if present.
1408 //
1409 if (SubClassEntry->LowerLevelClass == NULL) {
1410 *TextSubClass = SubClassEntry->DescText;
1411 return;
1412 }
1413
1414 Index = 0;
1415 InterfaceEntry = NULL;
1416 while (SubClassEntry->LowerLevelClass[Index].DescText != NULL) {
1417 if (SubClassEntry->LowerLevelClass[Index].Code == Interface) {
1418 InterfaceEntry = &SubClassEntry->LowerLevelClass[Index];
1419 break;
1420 }
1421
1422 Index++;
1423 }
1424
1425 if (InterfaceEntry == NULL) {
1426 *TextSubClass = SubClassEntry->DescText;
1427 return;
1428 }
1429
1430 *TextSubClass = InterfaceEntry->DescText;
1431}
1432
1433EFI_STATUS
1435 IN EFI_FILE_PROTOCOL *Root
1436 )
1437{
1438 EFI_STATUS Status;
1439 UINTN HandleCount;
1440 EFI_HANDLE *HandleBuffer;
1441 UINTN Index;
1442 EFI_PCI_IO_PROTOCOL *PciIo;
1443 PCI_TYPE00 PciDevice;
1444 CONST CHAR8 *TextPciClass;
1445 CONST CHAR8 *TextPciSubClass;
1446 EFI_DEVICE_PATH_PROTOCOL *PciDevicePath;
1447 CHAR16 *TextPciDevicePath;
1448
1449 CHAR8 *FileBuffer;
1450 UINTN FileBufferSize;
1451 CHAR16 TmpFileName[32];
1452
1453 ASSERT (Root != NULL);
1454
1455 FileBufferSize = SIZE_1KB;
1456 FileBuffer = AllocateZeroPool (FileBufferSize);
1457 if (FileBuffer == NULL) {
1458 return EFI_OUT_OF_RESOURCES;
1459 }
1460
1461 Status = gBS->LocateHandleBuffer (
1462 ByProtocol,
1463 &gEfiPciIoProtocolGuid,
1464 NULL,
1465 &HandleCount,
1466 &HandleBuffer
1467 );
1468 if (EFI_ERROR (Status)) {
1469 DEBUG ((DEBUG_INFO, "OCDM: No PCI devices found for dumping - %r\n", Status));
1470 FreePool (FileBuffer);
1471 return Status;
1472 }
1473
1474 for (Index = 0; Index < HandleCount; ++Index) {
1475 Status = gBS->HandleProtocol (
1476 HandleBuffer[Index],
1477 &gEfiPciIoProtocolGuid,
1478 (VOID **)&PciIo
1479 );
1480 if (EFI_ERROR (Status)) {
1481 continue;
1482 }
1483
1484 //
1485 // Read the whole PCI device in 32-bit.
1486 //
1487 Status = PciIo->Pci.Read (
1488 PciIo,
1489 EfiPciIoWidthUint32,
1490 0,
1491 sizeof (PCI_TYPE00) / sizeof (UINT32),
1492 &PciDevice
1493 );
1494 if (EFI_ERROR (Status)) {
1495 continue;
1496 }
1497
1498 //
1499 // Dump PCI class text.
1500 //
1502 PciDevice.Hdr.ClassCode[2],
1503 PciDevice.Hdr.ClassCode[1],
1504 PciDevice.Hdr.ClassCode[0],
1505 &TextPciClass,
1506 &TextPciSubClass
1507 );
1508 if (TextPciSubClass != NULL) {
1510 &FileBuffer,
1511 &FileBufferSize,
1512 "%02u. %a - %a",
1513 Index + 1,
1514 TextPciClass,
1515 TextPciSubClass
1516 );
1517 } else {
1519 &FileBuffer,
1520 &FileBufferSize,
1521 "%02u. %a",
1522 Index + 1,
1523 TextPciClass
1524 );
1525 }
1526
1527 //
1528 // Dump PCI info.
1529 //
1531 &FileBuffer,
1532 &FileBufferSize,
1533 "\n Vendor ID: 0x%04X, Device ID: 0x%04X, RevisionID: 0x%02X, ClassCode: 0x%02X%02X%02X",
1534 Index + 1,
1535 PciDevice.Hdr.VendorId,
1536 PciDevice.Hdr.DeviceId,
1537 PciDevice.Hdr.RevisionID,
1538 PciDevice.Hdr.ClassCode[2],
1539 PciDevice.Hdr.ClassCode[1],
1540 PciDevice.Hdr.ClassCode[0]
1541 );
1542 //
1543 // Dump SubsystemVendorID and SubsystemID if the current device is not a PCI bridge.
1544 //
1545 if (!IS_PCI_BRIDGE (&PciDevice)) {
1547 &FileBuffer,
1548 &FileBufferSize,
1549 ", SubsystemVendorID: 0x%04X, SubsystemID: 0x%04X",
1550 PciDevice.Device.SubsystemVendorID,
1551 PciDevice.Device.SubsystemID
1552 );
1553 }
1554
1555 //
1556 // Also dump device path if possible.
1557 //
1558 Status = gBS->HandleProtocol (
1559 HandleBuffer[Index],
1561 (VOID **)&PciDevicePath
1562 );
1563 if (!EFI_ERROR (Status)) {
1564 TextPciDevicePath = ConvertDevicePathToText (PciDevicePath, FALSE, FALSE);
1565 if (TextPciDevicePath != NULL) {
1567 &FileBuffer,
1568 &FileBufferSize,
1569 "\n DevicePath: %s",
1570 TextPciDevicePath
1571 );
1572
1573 FreePool (TextPciDevicePath);
1574 }
1575 }
1576
1577 //
1578 // Finally, append two newlines.
1579 //
1580 OcAsciiPrintBuffer (&FileBuffer, &FileBufferSize, "\n\n");
1581 }
1582
1583 //
1584 // Save dumped PCI info to file.
1585 //
1586 if (FileBuffer != NULL) {
1587 UnicodeSPrint (TmpFileName, sizeof (TmpFileName), L"PCIInfo.txt");
1588 Status = OcSetFileData (Root, TmpFileName, FileBuffer, (UINT32)AsciiStrLen (FileBuffer));
1589 DEBUG ((DEBUG_INFO, "OCDM: Dumped PCI info - %r\n", Status));
1590
1591 FreePool (FileBuffer);
1592 }
1593
1594 return EFI_SUCCESS;
1595}
#define ARRAY_SIZE(Array)
Definition AppleMacEfi.h:34
EFI_BOOT_SERVICES * gBS
EFI_STATUS OcSetFileData(IN EFI_FILE_PROTOCOL *WritableFs OPTIONAL, IN CONST CHAR16 *FileName, IN CONST VOID *Buffer, IN UINT32 Size)
VOID EFIAPI OcAsciiPrintBuffer(IN OUT CHAR8 **AsciiBuffer, IN OUT UINTN *AsciiBufferSize, IN CONST CHAR8 *FormatString,...)
Definition OcAsciiLib.c:510
STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage[]
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip00[]
STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage05[]
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip01[]
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip[]
STATIC CONST PCI_CLASS_ENTRY mPciClass02Network[]
STATIC CONST PCI_CLASS_ENTRY mPciClass05Memory[]
STATIC CONST PCI_CLASS_ENTRY mPciClass06Bridge[]
STATIC CONST PCI_CLASS_ENTRY mPciClass0CSerialBus[]
STATIC CONST PCI_CLASS_ENTRY mPciClass00PreClassCode[]
Definition PciInfoDump.c:45
STATIC CONST PCI_CLASS_ENTRY mPciClass0CSerialBus03[]
STATIC CONST PCI_CLASS_ENTRY mPciClass03Display[]
STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage09[]
STATIC CONST PCI_CLASS_ENTRY mPciClass04Multimedia[]
STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage06[]
EFI_STATUS OcPciInfoDump(IN EFI_FILE_PROTOCOL *Root)
STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms01[]
STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage00[]
Definition PciInfoDump.c:68
STATIC CONST PCI_CLASS_ENTRY mPciClass11DataAcquisition[]
STATIC CONST PCI_CLASS_ENTRY mPciClass0BProcessor[]
struct PCI_CLASS_ENTRY_TAG PCI_CLASS_ENTRY
STATIC CONST PCI_CLASS_ENTRY mPciClass09Input[]
STATIC CONST PCI_CLASS_ENTRY mPciClass0DWireless[]
STATIC CONST PCI_CLASS_ENTRY mPciClass03Display00[]
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip03[]
STATIC VOID GetPciDeviceClassText(IN UINT8 BaseClass, IN UINT8 SubClass, IN UINT8 Interface, OUT CONST CHAR8 **TextBaseClass, OUT CONST CHAR8 **TextSubClass)
STATIC CONST PCI_CLASS_ENTRY mPciClasses[]
STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms00[]
STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage08[]
STATIC CONST PCI_CLASS_ENTRY mPciClass10EncryptionDecryption[]
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip02[]
STATIC CONST PCI_CLASS_ENTRY mPciClass0CSerialBus00[]
STATIC CONST PCI_CLASS_ENTRY mPciClass0ADocking[]
STATIC CONST PCI_CLASS_ENTRY mPciClass0FSatellite[]
STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms[]
STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms03[]
EFI_GUID gEfiDevicePathProtocolGuid
#define ASSERT(x)
Definition coder.h:55
#define Code
Definition deflate.h:80
CONST CHAR8 * DescText
Definition PciInfoDump.c:34
CONST struct PCI_CLASS_ENTRY_TAG * LowerLevelClass
Definition PciInfoDump.c:35