9#include <Library/IoLib.h>
10#include <Library/PrintLib.h>
11#include <Library/BaseLib.h>
12#include <Library/BaseMemoryLib.h>
13#include <Library/DebugLib.h>
15#include <Library/TimerLib.h>
16#include <Library/UefiApplicationEntryPoint.h>
17#include <Library/UefiBootServicesTableLib.h>
18#include <Library/UefiLib.h>
22#define PTT_HCI_TIMEOUT_A 500
23#define PTT_HCI_POLLING_PERIOD 140
33 OUT UINT32 *Value OPTIONAL
42 for (Waited = 0; Waited < Timeout; Waited += Period) {
45 if (Tmp == 0xFFFFFFFF) {
50 if (((Tmp & BitSet) == BitSet) && ((Tmp & BitClear) == 0)) {
81 if (EFI_ERROR (Status)) {
82 DEBUG ((DEBUG_WARN,
"TPM: No HECI protocol %r\n", Status));
94 (UINT32 *)&MsgGenGetFwCapsSku,
100 if (EFI_ERROR (Status)) {
101 DEBUG ((DEBUG_WARN,
"TPM: HECI failed to write %r\n", Status));
105 ZeroMem (&MsgGenGetFwCapsSkuAck,
sizeof (MsgGenGetFwCapsSkuAck));
107 Length =
sizeof (MsgGenGetFwCapsSkuAck);
110 (UINT32 *)&MsgGenGetFwCapsSkuAck,
114 if (EFI_ERROR (Status)) {
115 DEBUG ((DEBUG_WARN,
"TPM: HECI failed to read %r\n", Status));
124 DEBUG ((DEBUG_WARN,
"TPM: HECI PCH supports TPM\n"));
128 DEBUG ((DEBUG_WARN,
"TPM: HECI PCH does NOT support TPM\n"));
129 return EFI_UNSUPPORTED;
132 DEBUG ((DEBUG_WARN,
"TPM: HECI got invalid response\n"));
133 return EFI_INVALID_PARAMETER;
139 IN EFI_HANDLE ImageHandle,
140 IN EFI_SYSTEM_TABLE *SystemTable
145 DEBUG ((DEBUG_WARN,
"TPM: Will now verify fTPM (PTT) availability\n"));
149 DEBUG ((DEBUG_WARN,
"TPM: HECI returned %r\n", Status));
162 "TPM: Discovered status at 0x%08X is %r\n",
178 "TPM: Discovered status at 0x%08X is %r\n",
struct _GEN_GET_FW_CAPSKU GEN_GET_FW_CAPSKU
#define HECI_CORE_MESSAGE_ADDR
#define BIOS_FIXED_HOST_ADDR
#define FWCAPS_GET_RULE_CMD
EFI_STATUS HeciReadMessage(IN UINT32 Blocking, IN UINT32 *MessageBody, IN OUT UINT32 *Length)
EFI_STATUS HeciLocateProtocol(VOID)
EFI_STATUS HeciSendMessage(IN UINT32 *Message, IN UINT32 Length, IN UINT8 HostAddress, IN UINT8 MEAddress)
#define B_CRB_CONTROL_STS_TPM_STATUS
BIT0.
#define R_PTT_HCI_BASE_ADDRESS_A
#define V_PTT_HCI_IGNORE_BITS
#define R_CRB_CONTROL_STS
#define R_PTT_HCI_BASE_ADDRESS_B
EFI_STATUS EFIAPI UefiMain(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
STATIC EFI_STATUS MmioRead32Timeout(IN UINTN Address, IN UINT32 BitSet, IN UINT32 BitClear, IN UINT32 Period, IN UINT32 Timeout, OUT UINT32 *Value OPTIONAL)
#define PTT_HCI_TIMEOUT_A
Timeout after 500 microseconds.
STATIC EFI_STATUS CheckHeci(VOID)
#define PTT_HCI_POLLING_PERIOD
Poll register every 140 microseconds.
VOID *EFIAPI ZeroMem(OUT VOID *Buffer, IN UINTN Length)
UINT32 EFIAPI MmioRead32(IN UINTN Address)
UINTN EFIAPI MicroSecondDelay(IN UINTN MicroSeconds)
GEN_GET_FW_CAPS_SKU_ACK_DATA Data
MKHI_MESSAGE_HEADER MKHIHeader
MKHI_MESSAGE_HEADER MKHIHeader
struct _MKHI_MESSAGE_HEADER::@64 Fields
UINT32 PTT
[29] Platform Trust Technoogy (PTT)
struct _SECFWCAPS_SKU::@67 Fields