18#include <Library/BaseLib.h>
27 IN CONST CHAR8 *BrandString
30 CONST CHAR8 *BrandInfix;
32 BrandInfix = AsciiStrStr (BrandString,
"Core");
33 if (BrandInfix != NULL) {
34 while ((*BrandInfix !=
' ') && (*BrandInfix !=
'\0')) {
38 while (*BrandInfix ==
' ') {
42 if (AsciiStrnCmp (BrandInfix,
"i7",
L_STR_LEN (
"i7")) == 0) {
46 if (AsciiStrnCmp (BrandInfix,
"i5",
L_STR_LEN (
"i5")) == 0) {
50 if (AsciiStrnCmp (BrandInfix,
"i3",
L_STR_LEN (
"i3")) == 0) {
54 if (AsciiStrnCmp (BrandInfix,
"i9",
L_STR_LEN (
"i9")) == 0) {
58 if (AsciiStrnCmp (BrandInfix,
"m3",
L_STR_LEN (
"m3")) == 0) {
62 if (AsciiStrnCmp (BrandInfix,
"m5",
L_STR_LEN (
"m5")) == 0) {
66 if (AsciiStrnCmp (BrandInfix,
"m7",
L_STR_LEN (
"m7")) == 0) {
70 if (AsciiStrnCmp (BrandInfix,
"M",
L_STR_LEN (
"M")) == 0) {
74 if (AsciiStrnCmp (BrandInfix,
"Duo",
L_STR_LEN (
"Duo")) == 0) {
78 if (AsciiStrnCmp (BrandInfix,
"Quad",
L_STR_LEN (
"Quad")) == 0) {
85 BrandInfix = AsciiStrStr (BrandString,
"Xeon");
86 if (BrandInfix != NULL) {
87 while ((*BrandInfix !=
' ') && (*BrandInfix !=
'\0')) {
91 while (*BrandInfix ==
' ') {
98 if ((AsciiStrnCmp (BrandInfix,
"Bronze",
L_STR_LEN (
"Bronze")) == 0) ||
99 (AsciiStrnCmp (BrandInfix,
"Silver",
L_STR_LEN (
"Silver")) == 0) ||
100 (AsciiStrnCmp (BrandInfix,
"Gold",
L_STR_LEN (
"Gold")) == 0) ||
101 (AsciiStrnCmp (BrandInfix,
"Platinum",
L_STR_LEN (
"Platinum")) == 0))
110 if (AsciiStrnCmp (BrandInfix,
"CPU",
L_STR_LEN (
"CPU")) == 0) {
112 while (*BrandInfix ==
' ') {
117 if (AsciiStrnCmp (BrandInfix,
"E5-",
L_STR_LEN (
"E5-")) == 0) {
121 if (AsciiStrnCmp (BrandInfix,
"W-",
L_STR_LEN (
"W-")) == 0) {
135 IN UINT8 AppleMajorType,
687 IN CPUID_VERSION_INFO_EAX VersionEax
692 if (VersionEax.Bits.FamilyId != 6) {
700 Model = (UINT8)VersionEax.Bits.Model | (UINT8)(VersionEax.Bits.ExtendedModelId << 4U);
752 MhzSpeed = (UINT16)
DivU64x32 (Frequency + 500000, 1000000);
753 MhzRemainder = MhzSpeed % 100;
758 if ((MhzRemainder >= 60) && (MhzRemainder < 89)) {
759 MhzSpeed = (MhzSpeed) / 10 * 10;
760 }
else if ((MhzRemainder >= 12) && (MhzRemainder < 89)) {
761 MhzSpeed = (MhzSpeed + 5) / 10 * 10;
763 MhzSpeed = (MhzSpeed + 50) / 100 * 100;
UINT16 InternalDetectAppleProcessorType(IN UINT8 Model, IN UINT8 Stepping, IN UINT8 AppleMajorType, IN UINT16 CoreCount, IN BOOLEAN Is64Bit)
UINT32 OcCpuModelToAppleFamily(IN CPUID_VERSION_INFO_EAX VersionEax)
UINT8 InternalDetectAppleMajorType(IN CONST CHAR8 *BrandString)
UINT16 OcCpuFrequencyToDisplayFrequency(IN UINT64 Frequency)
#define CPUFAMILY_UNKNOWN
#define CPUFAMILY_INTEL_SANDYBRIDGE
#define CPUFAMILY_INTEL_KABYLAKE
#define CPUFAMILY_INTEL_PENRYN
#define CPUFAMILY_INTEL_WESTMERE
#define CPUFAMILY_INTEL_HASWELL
#define CPUFAMILY_INTEL_SKYLAKE
#define CPUFAMILY_INTEL_BROADWELL
#define CPUFAMILY_INTEL_NEHALEM
#define CPUFAMILY_INTEL_IVYBRIDGE
@ AppleProcessorTypeXeonW
@ AppleProcessorTypeCorei5Type9
@ AppleProcessorTypeCorei3Type1
@ AppleProcessorTypeCorei5Type3
@ AppleProcessorTypeCorei3Type4
@ AppleProcessorTypeCorei7Type4
@ AppleProcessorTypeXeonE5
@ AppleProcessorTypeCorei7Type9
@ AppleProcessorTypeCoreMType6
@ AppleProcessorTypeCore2DuoType2
@ AppleProcessorTypeCorei7Type5
@ AppleProcessorTypeCorei5Type2
@ AppleProcessorTypeCorei7Type3
@ AppleProcessorTypeCoreM5Type7
@ AppleProcessorTypeCoreSolo
@ AppleProcessorTypeCore2DuoType1
@ AppleProcessorTypeCorei9Type5
@ AppleProcessorTypeCorei3Type3
@ AppleProcessorTypeCorei7Type2
@ AppleProcessorTypeCorei5Type6
@ AppleProcessorTypeCorei9Type9
@ AppleProcessorTypeCoreM3Type7
@ AppleProcessorTypeCoreM7Type7
@ AppleProcessorTypeCorei3Type6
@ AppleProcessorTypeXeonPenrynType2
@ AppleProcessorTypeCorei5Type5
@ AppleProcessorTypeCorei5Type4
@ AppleProcessorTypeCorei3Type5
@ AppleProcessorTypeCorei7Type6
@ AppleProcessorMajorXeonPenryn
@ AppleProcessorMajorXeonNehalem
@ AppleProcessorMajorUnknown
@ AppleProcessorMajorCore
@ AppleProcessorMajorXeonE5
@ AppleProcessorMajorCore2
@ AppleProcessorMajorXeonW
#define L_STR_LEN(String)
#define CPU_MODEL_PRESCOTT
Prescott, Nocona, Cranford, Potomac.
#define CPU_MODEL_SKYLAKE_W
#define CPU_MODEL_IVYBRIDGE_EP
#define CPU_MODEL_TIGERLAKE_U
#define CPU_MODEL_MEROM
Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom.
#define CPU_MODEL_IVYBRIDGE
Ivy Bridge.
#define CPU_MODEL_ARROWLAKE_U
#define CPU_MODEL_ROCKETLAKE_S
desktop RocketLake
#define CPU_MODEL_SKYLAKE_DT
#define CPU_MODEL_SALTWELL
Saltwell, Cedarview.
#define CPU_MODEL_BANIAS
Banias.
#define CPU_MODEL_ARROWLAKE_S
desktop ArrowLake
#define CPU_MODEL_ARROWLAKE_HX
#define CPU_MODEL_RAPTORLAKE_S
Raptor Lake B0 stepping.
#define CPU_MODEL_JAKETOWN
Sandy Bridge Xeon E5, Core i7 Extreme.
#define CPU_MODEL_YONAH
Sossaman, Yonah.
#define CPU_MODEL_PRESCOTT_2M
Prescott 2M, Smithfield, Irwindale, Paxville.
#define CPU_MODEL_BROADWELL_EP
Broadwell_EP.
#define CPU_MODEL_COMETLAKE_S
desktop CometLake
#define CPU_MODEL_NEHALEM
Bloomfield, Nehalem-EP, Nehalem-WS, Gainestown.
#define CPU_MODEL_COFFEELAKE
#define CPU_MODEL_COMETLAKE_U
#define CPU_MODEL_BRYSTALWELL
#define CPU_MODEL_ICELAKE_U
#define CPU_MODEL_HASWELL
#define CPU_MODEL_CRYSTALWELL
#define CPU_MODEL_WESTMERE
Gulftown, Westmere-EP, Westmere-WS.
#define CPU_MODEL_WESTMERE_EX
#define CPU_MODEL_HASWELL_ULT
Haswell ULT.
#define CPU_MODEL_ICELAKE_Y
#define CPU_MODEL_NORTHWOOD
Northwood, Prestonia, Gallatin.
#define CPU_MODEL_PENRYN
Wolfdale, Yorkfield, Harpertown, Penryn.
#define CPU_MODEL_RAPTORLAKE_HX
Raptor Lake C0 stepping.
#define CPU_MODEL_HASWELL_EP
Haswell MB.
#define CPU_MODEL_SKYLAKE
Skylake-S.
#define CPU_MODEL_CEDAR_MILL
Cedar Mill, Presler, Tusla, Dempsey.
#define CPU_MODEL_FIELDS
Lynnfield, Clarksfield, Jasper Forest.
#define CPU_MODEL_NEHALEM_EX
Beckton.
#define CPU_MODEL_WILLAMETTE
Willamette, Foster.
#define CPU_MODEL_DALES_32NM
Clarkdale, Arrandale.
#define CPU_MODEL_ALDERLAKE_S
#define CPU_MODEL_ICELAKE_SP
Some variation of Ice Lake.
#define CPU_MODEL_DOTHAN
Dothan.
#define CPU_MODEL_BONNELL
Bonnell, Silverthorne, Diamondville, Pineview.
#define CPU_MODEL_BROADWELL
Broadwell.
#define CPU_MODEL_KABYLAKE_DT
#define CPU_MODEL_KABYLAKE
Kabylake Dektop.
#define CPU_MODEL_DALES
Havendale, Auburndale.
#define CPU_MODEL_BONNELL_MID
Bonnell, Lincroft.
#define CPU_MODEL_SANDYBRIDGE
Sandy Bridge.
#define DivU64x32(x, y, z)