Macros
#define	BRIDGE_BCLK 100

#define	BASE_NHM_CLOCK_SOURCE 133333333ULL

#define	CLIENT_ART_CLOCK_SOURCE 24000000ULL

#define	SERVER_ART_CLOCK_SOURCE 25000000ULL

#define	ATOM_ART_CLOCK_SOURCE 19200000ULL

#define	DEFAULT_ART_CLOCK_SOURCE CLIENT_ART_CLOCK_SOURCE

#define	MSR_PIC_MSG_CONTROL 0x2E

#define	MSR_CORE_THREAD_COUNT 0x35

#define	EFI_PLATFORM_INFORMATION 0x000000CE

#define	N_EFI_PLATFORM_INFO_MIN_RATIO 40

#define	B_EFI_PLATFORM_INFO_RATIO_MASK 0xFF

#define	N_EFI_PLATFORM_INFO_MAX_RATIO 8

#define	B_EFI_PLATFORM_INFO_TDC_TDP_LIMIT (1 << 29)

#define	N_EFI_PLATFORM_INFO_RATIO_LIMIT 28

#define	B_EFI_PLATFORM_INFO_RATIO_LIMIT (1 << 28)

#define	B_EFI_PLATFORM_INFO_SMM_SAVE_CONTROL (1 << 16)

#define	N_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30

#define	B_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET (1 << 30)

#define	MSR_PMG_IO_CAPTURE_BASE 0xE4

#define	MSR_IA32_EXT_CONFIG 0xEE

#define	MSR_FEATURE_CONFIG 0x13C

#define	MSR_FLEX_RATIO 0x194

#define	FLEX_RATIO_LOCK (1U << 20U)

#define	FLEX_RATIO_EN (1U << 16U)

#define	MSR_IA32_PERF_CONTROL 0x199

#define	MSR_THERM2_CTL 0x19D

#define	TURBO_DISABLE_MASK ((UINT64)1 << 38)

#define	TURBO_MODE_DISABLE_BIT 38

#define	MSR_TEMPERATURE_TARGET 0x1A2

#define	MSR_MISC_PWR_MGMT 0x1AA

#define	MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)

#define	MISC_PWR_MGMT_LOCK (1 << 13)

#define	MAX_RATIO_LIMIT_8C_OFFSET 56

#define	MAX_RATIO_LIMIT_7C_OFFSET 48

#define	MAX_RATIO_LIMIT_6C_OFFSET 40

#define	MAX_RATIO_LIMIT_5C_OFFSET 32

#define	MAX_RATIO_LIMIT_4C_OFFSET 24

#define	MAX_RATIO_LIMIT_3C_OFFSET 16

#define	MAX_RATIO_LIMIT_2C_OFFSET 8

#define	MAX_RATIO_LIMIT_1C_OFFSET 0

#define	MAX_RATIO_LIMIT_MASK 0xff

#define	MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1B0

#define	ENERGY_POLICY_PERFORMANCE 0

#define	ENERGY_POLICY_NORMAL 6

#define	ENERGY_POLICY_POWERSAVE 15

#define	MSR_POWER_CTL 0x1FC

#define	MSR_LT_LOCK_MEMORY 0x2E7

#define	MSR_IA32_CR_PAT 0x277

#define	MSR_PP0_CURRENT_CONFIG 0x601

#define	PP0_CURRENT_LIMIT (112 << 3)
	112 A

#define	MSR_PP1_CURRENT_CONFIG 0x602

#define	PP1_CURRENT_LIMIT (35 << 3)
	35 A

#define	MSR_PKG_POWER_SKU_UNIT 0x606

#define	MSR_PKGC3_IRTL 0x60A

#define	MSR_PKGC6_IRTL 0x60B

#define	MSR_PKGC7_IRTL 0x60C

#define	IRTL_VALID (1 << 15)

#define	IRTL_1_NS (0 << 10)

#define	IRTL_32_NS (1 << 10)

#define	IRTL_1024_NS (2 << 10)

#define	IRTL_32768_NS (3 << 10)

#define	IRTL_1048576_NS (4 << 10)

#define	IRTL_33554432_NS (5 << 10)

#define	IRTL_RESPONSE_MASK (0x3ff)

#define	MSR_PKG_POWER_LIMIT 0x610

#define	PKG_POWER_LIMIT_MASK 0x7fff

#define	PKG_POWER_LIMIT_EN (1 << 15)

#define	PKG_POWER_LIMIT_CLAMP (1 << 16)

#define	PKG_POWER_LIMIT_TIME_SHIFT 17

#define	PKG_POWER_LIMIT_TIME_MASK 0x7f

#define	MSR_PKG_ENERGY_STATUS 0x611

#define	MSR_PKG_PERF_STATUS 0x613

#define	MSR_PKG_POWER_SKU 0x614

#define	MSR_PP0_POWER_LIMIT 0x638

#define	MSR_PP0_ENERGY_STATUS 0x639

#define	MSR_PP0_POLICY 0x63A

#define	MSR_PP0_PERF_STATUS 0x63B

#define	MSR_PP1_POWER_LIMIT 0x640

#define	MSR_PP1_ENERGY_STATUS 0x641

#define	MSR_PP1_POLICY 0x642

#define	MSR_DRAM_POWER_LIMIT 0x618

#define	MSR_DRAM_ENERGY_STATUS 0x619

#define	MSR_DRAM_PERF_STATUS 0x61B

#define	MSR_DRAM_POWER_INFO 0x61C

#define	PAT_ENTRY_BIT_MASK (0xFFU)

#define	PAT_INDEX_MAX 8

#define	SET_PAT_N(PatIndex, PatType)

#define	GET_PAT_N(PatMsr, PatIndex)

#define	MODIFY_PAT_MSR(PatMsr, PatIndex, PatType)

#define	PAT_DEFAULTS

#define	K8_FIDVID_STATUS 0xC0010042

#define	K10_COFVID_STATUS 0xC0010071

#define	K10_PSTATE_STATUS 0xC0010064

#define	CPU_MODEL_WILLAMETTE 0x01
	Willamette, Foster.

#define	CPU_MODEL_NORTHWOOD 0x02
	Northwood, Prestonia, Gallatin.

#define	CPU_MODEL_PRESCOTT 0x03
	Prescott, Nocona, Cranford, Potomac.

#define	CPU_MODEL_PRESCOTT_2M 0x04
	Prescott 2M, Smithfield, Irwindale, Paxville.

#define	CPU_MODEL_CEDAR_MILL 0x06
	Cedar Mill, Presler, Tusla, Dempsey.

#define	CPU_MODEL_BANIAS 0x09
	Banias.

#define	CPU_MODEL_DOTHAN 0x0D
	Dothan.

#define	CPU_MODEL_YONAH 0x0E
	Sossaman, Yonah.

#define	CPU_MODEL_MEROM 0x0F
	Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom.

#define	CPU_MODEL_PENRYN 0x17
	Wolfdale, Yorkfield, Harpertown, Penryn.

#define	CPU_MODEL_NEHALEM 0x1A
	Bloomfield, Nehalem-EP, Nehalem-WS, Gainestown.

#define	CPU_MODEL_BONNELL 0x1C
	Bonnell, Silverthorne, Diamondville, Pineview.

#define	CPU_MODEL_FIELDS 0x1E
	Lynnfield, Clarksfield, Jasper Forest.

#define	CPU_MODEL_DALES 0x1F
	Havendale, Auburndale.

#define	CPU_MODEL_NEHALEM_EX 0x2E
	Beckton.

#define	CPU_MODEL_DALES_32NM 0x25
	Clarkdale, Arrandale.

#define	CPU_MODEL_BONNELL_MID 0x26
	Bonnell, Lincroft.

#define	CPU_MODEL_WESTMERE 0x2C
	Gulftown, Westmere-EP, Westmere-WS.

#define	CPU_MODEL_WESTMERE_EX 0x2F

#define	CPU_MODEL_SANDYBRIDGE 0x2A
	Sandy Bridge.

#define	CPU_MODEL_JAKETOWN 0x2D
	Sandy Bridge Xeon E5, Core i7 Extreme.

#define	CPU_MODEL_SALTWELL 0x36
	Saltwell, Cedarview.

#define	CPU_MODEL_SILVERMONT 0x37
	Bay Trail.

#define	CPU_MODEL_IVYBRIDGE 0x3A
	Ivy Bridge.

#define	CPU_MODEL_IVYBRIDGE_EP 0x3E

#define	CPU_MODEL_CRYSTALWELL 0x46

#define	CPU_MODEL_HASWELL 0x3C

#define	CPU_MODEL_HASWELL_EP 0x3F
	Haswell MB.

#define	CPU_MODEL_HASWELL_ULT 0x45
	Haswell ULT.

#define	CPU_MODEL_BROADWELL 0x3D
	Broadwell.

#define	CPU_MODEL_BROADWELL_EP 0x4F
	Broadwell_EP.

#define	CPU_MODEL_BROADWELL_ULX 0x3D

#define	CPU_MODEL_BROADWELL_ULT 0x3D

#define	CPU_MODEL_BRYSTALWELL 0x47

#define	CPU_MODEL_AIRMONT 0x4C
	CherryTrail / Braswell.

#define	CPU_MODEL_AVOTON 0x4D
	Avaton/Rangely.

#define	CPU_MODEL_SKYLAKE 0x4E
	Skylake-S.

#define	CPU_MODEL_SKYLAKE_ULT 0x4E

#define	CPU_MODEL_SKYLAKE_ULX 0x4E

#define	CPU_MODEL_SKYLAKE_DT 0x5E

#define	CPU_MODEL_SKYLAKE_W 0x55

#define	CPU_MODEL_GOLDMONT 0x5C
	Apollo Lake.

#define	CPU_MODEL_DENVERTON 0x5F
	Goldmont Microserver.

#define	CPU_MODEL_CANNONLAKE 0x66

#define	CPU_MODEL_XEON_MILL 0x85
	Knights Mill.

#define	CPU_MODEL_KABYLAKE 0x8E
	Kabylake Dektop.

#define	CPU_MODEL_KABYLAKE_ULT 0x8E

#define	CPU_MODEL_KABYLAKE_ULX 0x8E

#define	CPU_MODEL_KABYLAKE_DT 0x9E

#define	CPU_MODEL_COFFEELAKE 0x9E

#define	CPU_MODEL_COFFEELAKE_ULT 0x9E

#define	CPU_MODEL_COFFEELAKE_ULX 0x9E

#define	CPU_MODEL_COFFEELAKE_DT 0x9E

#define	CPU_MODEL_ICELAKE_Y 0x7D

#define	CPU_MODEL_ICELAKE_U 0x7E

#define	CPU_MODEL_ICELAKE_SP 0x9F
	Some variation of Ice Lake.

#define	CPU_MODEL_COMETLAKE_S 0xA5
	desktop CometLake

#define	CPU_MODEL_COMETLAKE_Y 0xA5
	aka 10th generation Amber Lake Y

#define	CPU_MODEL_COMETLAKE_U 0xA6

#define	CPU_MODEL_ROCKETLAKE_S 0xA7
	desktop RocketLake

#define	CPU_MODEL_TIGERLAKE_U 0x8C

#define	CPU_MODEL_ALDERLAKE_S 0x97

#define	CPU_MODEL_RAPTORLAKE_S 0xB7
	Raptor Lake B0 stepping.

#define	CPU_MODEL_RAPTORLAKE_HX 0xBF
	Raptor Lake C0 stepping.

#define	CPU_MODEL_ARROWLAKE_S 0xC6
	desktop ArrowLake

#define	CPU_MODEL_ARROWLAKE_HX 0xC5

#define	CPU_MODEL_ARROWLAKE_U 0xB5

#define	AMD_CPU_FAMILY 0xF

#define	AMD_CPU_EXT_FAMILY_0FH 0x0

#define	AMD_CPU_EXT_FAMILY_10H 0x1

#define	AMD_CPU_EXT_FAMILY_15H 0x6

#define	AMD_CPU_EXT_FAMILY_16H 0x7

#define	AMD_CPU_EXT_FAMILY_17H 0x8

#define	AMD_CPU_EXT_FAMILY_19H 0xA

#define	AMD_CPU_EXT_FAMILY_1AH 0xB

Enumerations
enum	PAT_MEMORY_CACHE_TYPE { PatUncacheable = 0 , PatWriteCombining = 1 , PatWriteThrough = 4 , PatWriteProtected = 5 , PatWriteBack = 6 , PatUncached = 7 }

enum	CPU_P_STATE_COORDINATION { CpuPStateCoordinationSoftwareAll = 0xFC , CpuPStateCoordinationSoftwareAny = 0xFD , CpuPStateCoordinationHardwareAll = 0xFE }
	P-State Coordination. More...

Detailed Description

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ProcessorInfo.h.

Macro Definition Documentation

◆ AMD_CPU_EXT_FAMILY_0FH

#define AMD_CPU_EXT_FAMILY_0FH 0x0

Definition at line 258 of file ProcessorInfo.h.

◆ AMD_CPU_EXT_FAMILY_10H

#define AMD_CPU_EXT_FAMILY_10H 0x1

Definition at line 259 of file ProcessorInfo.h.

◆ AMD_CPU_EXT_FAMILY_15H

#define AMD_CPU_EXT_FAMILY_15H 0x6

Definition at line 260 of file ProcessorInfo.h.

◆ AMD_CPU_EXT_FAMILY_16H

#define AMD_CPU_EXT_FAMILY_16H 0x7

Definition at line 261 of file ProcessorInfo.h.

◆ AMD_CPU_EXT_FAMILY_17H

#define AMD_CPU_EXT_FAMILY_17H 0x8

Definition at line 262 of file ProcessorInfo.h.

◆ AMD_CPU_EXT_FAMILY_19H

#define AMD_CPU_EXT_FAMILY_19H 0xA

Definition at line 263 of file ProcessorInfo.h.

◆ AMD_CPU_EXT_FAMILY_1AH

#define AMD_CPU_EXT_FAMILY_1AH 0xB

Definition at line 264 of file ProcessorInfo.h.

◆ AMD_CPU_FAMILY

#define AMD_CPU_FAMILY 0xF

Definition at line 257 of file ProcessorInfo.h.

◆ ATOM_ART_CLOCK_SOURCE

#define ATOM_ART_CLOCK_SOURCE 19200000ULL

Definition at line 30 of file ProcessorInfo.h.

◆ B_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET

#define B_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET (1 << 30)

Definition at line 46 of file ProcessorInfo.h.

◆ B_EFI_PLATFORM_INFO_RATIO_LIMIT

#define B_EFI_PLATFORM_INFO_RATIO_LIMIT (1 << 28)

Definition at line 43 of file ProcessorInfo.h.

◆ B_EFI_PLATFORM_INFO_RATIO_MASK

#define B_EFI_PLATFORM_INFO_RATIO_MASK 0xFF

Definition at line 39 of file ProcessorInfo.h.

◆ B_EFI_PLATFORM_INFO_SMM_SAVE_CONTROL

#define B_EFI_PLATFORM_INFO_SMM_SAVE_CONTROL (1 << 16)

Definition at line 44 of file ProcessorInfo.h.

◆ B_EFI_PLATFORM_INFO_TDC_TDP_LIMIT

#define B_EFI_PLATFORM_INFO_TDC_TDP_LIMIT (1 << 29)

Definition at line 41 of file ProcessorInfo.h.

◆ BASE_NHM_CLOCK_SOURCE

#define BASE_NHM_CLOCK_SOURCE 133333333ULL

Definition at line 22 of file ProcessorInfo.h.

◆ BRIDGE_BCLK

#define BRIDGE_BCLK 100

Definition at line 20 of file ProcessorInfo.h.

◆ CLIENT_ART_CLOCK_SOURCE

#define CLIENT_ART_CLOCK_SOURCE 24000000ULL

Definition at line 28 of file ProcessorInfo.h.

◆ CPU_MODEL_AIRMONT

#define CPU_MODEL_AIRMONT 0x4C

CherryTrail / Braswell.

Definition at line 223 of file ProcessorInfo.h.

◆ CPU_MODEL_ALDERLAKE_S

#define CPU_MODEL_ALDERLAKE_S 0x97

Definition at line 250 of file ProcessorInfo.h.

◆ CPU_MODEL_ARROWLAKE_HX

#define CPU_MODEL_ARROWLAKE_HX 0xC5

Definition at line 254 of file ProcessorInfo.h.

◆ CPU_MODEL_ARROWLAKE_S

#define CPU_MODEL_ARROWLAKE_S 0xC6

desktop ArrowLake

Definition at line 253 of file ProcessorInfo.h.

◆ CPU_MODEL_ARROWLAKE_U

#define CPU_MODEL_ARROWLAKE_U 0xB5

Definition at line 255 of file ProcessorInfo.h.

◆ CPU_MODEL_AVOTON

#define CPU_MODEL_AVOTON 0x4D

Avaton/Rangely.

Definition at line 224 of file ProcessorInfo.h.

◆ CPU_MODEL_BANIAS

#define CPU_MODEL_BANIAS 0x09

Banias.

Definition at line 194 of file ProcessorInfo.h.

◆ CPU_MODEL_BONNELL

#define CPU_MODEL_BONNELL 0x1C

Bonnell, Silverthorne, Diamondville, Pineview.

Definition at line 200 of file ProcessorInfo.h.

◆ CPU_MODEL_BONNELL_MID

#define CPU_MODEL_BONNELL_MID 0x26

Bonnell, Lincroft.

Definition at line 205 of file ProcessorInfo.h.

◆ CPU_MODEL_BROADWELL

#define CPU_MODEL_BROADWELL 0x3D

Broadwell.

Definition at line 218 of file ProcessorInfo.h.

◆ CPU_MODEL_BROADWELL_EP

#define CPU_MODEL_BROADWELL_EP 0x4F

Broadwell_EP.

Definition at line 219 of file ProcessorInfo.h.

◆ CPU_MODEL_BROADWELL_ULT

#define CPU_MODEL_BROADWELL_ULT 0x3D

Definition at line 221 of file ProcessorInfo.h.

◆ CPU_MODEL_BROADWELL_ULX

#define CPU_MODEL_BROADWELL_ULX 0x3D

Definition at line 220 of file ProcessorInfo.h.

◆ CPU_MODEL_BRYSTALWELL

#define CPU_MODEL_BRYSTALWELL 0x47

Definition at line 222 of file ProcessorInfo.h.

◆ CPU_MODEL_CANNONLAKE

#define CPU_MODEL_CANNONLAKE 0x66

Definition at line 232 of file ProcessorInfo.h.

◆ CPU_MODEL_CEDAR_MILL

#define CPU_MODEL_CEDAR_MILL 0x06

Cedar Mill, Presler, Tusla, Dempsey.

Definition at line 193 of file ProcessorInfo.h.

◆ CPU_MODEL_COFFEELAKE

#define CPU_MODEL_COFFEELAKE 0x9E

Definition at line 238 of file ProcessorInfo.h.

◆ CPU_MODEL_COFFEELAKE_DT

#define CPU_MODEL_COFFEELAKE_DT 0x9E

Definition at line 241 of file ProcessorInfo.h.

◆ CPU_MODEL_COFFEELAKE_ULT

#define CPU_MODEL_COFFEELAKE_ULT 0x9E

Definition at line 239 of file ProcessorInfo.h.

◆ CPU_MODEL_COFFEELAKE_ULX

#define CPU_MODEL_COFFEELAKE_ULX 0x9E

Definition at line 240 of file ProcessorInfo.h.

◆ CPU_MODEL_COMETLAKE_S

#define CPU_MODEL_COMETLAKE_S 0xA5

desktop CometLake

Definition at line 245 of file ProcessorInfo.h.

◆ CPU_MODEL_COMETLAKE_U

#define CPU_MODEL_COMETLAKE_U 0xA6

Definition at line 247 of file ProcessorInfo.h.

◆ CPU_MODEL_COMETLAKE_Y

#define CPU_MODEL_COMETLAKE_Y 0xA5

aka 10th generation Amber Lake Y

Definition at line 246 of file ProcessorInfo.h.

◆ CPU_MODEL_CRYSTALWELL

#define CPU_MODEL_CRYSTALWELL 0x46

Definition at line 214 of file ProcessorInfo.h.

◆ CPU_MODEL_DALES

#define CPU_MODEL_DALES 0x1F

Havendale, Auburndale.

Definition at line 202 of file ProcessorInfo.h.

◆ CPU_MODEL_DALES_32NM

#define CPU_MODEL_DALES_32NM 0x25

Clarkdale, Arrandale.

Definition at line 204 of file ProcessorInfo.h.

◆ CPU_MODEL_DENVERTON

#define CPU_MODEL_DENVERTON 0x5F

Goldmont Microserver.

Definition at line 231 of file ProcessorInfo.h.

◆ CPU_MODEL_DOTHAN

#define CPU_MODEL_DOTHAN 0x0D

Dothan.

Definition at line 195 of file ProcessorInfo.h.

◆ CPU_MODEL_FIELDS

#define CPU_MODEL_FIELDS 0x1E

Lynnfield, Clarksfield, Jasper Forest.

Definition at line 201 of file ProcessorInfo.h.

◆ CPU_MODEL_GOLDMONT

#define CPU_MODEL_GOLDMONT 0x5C

Apollo Lake.

Definition at line 230 of file ProcessorInfo.h.

◆ CPU_MODEL_HASWELL

#define CPU_MODEL_HASWELL 0x3C

Definition at line 215 of file ProcessorInfo.h.

◆ CPU_MODEL_HASWELL_EP

#define CPU_MODEL_HASWELL_EP 0x3F

Haswell MB.

Definition at line 216 of file ProcessorInfo.h.

◆ CPU_MODEL_HASWELL_ULT

#define CPU_MODEL_HASWELL_ULT 0x45

Haswell ULT.

Definition at line 217 of file ProcessorInfo.h.

◆ CPU_MODEL_ICELAKE_SP

#define CPU_MODEL_ICELAKE_SP 0x9F

Some variation of Ice Lake.

Definition at line 244 of file ProcessorInfo.h.

◆ CPU_MODEL_ICELAKE_U

#define CPU_MODEL_ICELAKE_U 0x7E

Definition at line 243 of file ProcessorInfo.h.

◆ CPU_MODEL_ICELAKE_Y

#define CPU_MODEL_ICELAKE_Y 0x7D

Definition at line 242 of file ProcessorInfo.h.

◆ CPU_MODEL_IVYBRIDGE

#define CPU_MODEL_IVYBRIDGE 0x3A

Ivy Bridge.

Definition at line 212 of file ProcessorInfo.h.

◆ CPU_MODEL_IVYBRIDGE_EP

#define CPU_MODEL_IVYBRIDGE_EP 0x3E

Definition at line 213 of file ProcessorInfo.h.

◆ CPU_MODEL_JAKETOWN

#define CPU_MODEL_JAKETOWN 0x2D

Sandy Bridge Xeon E5, Core i7 Extreme.

Definition at line 209 of file ProcessorInfo.h.

◆ CPU_MODEL_KABYLAKE

#define CPU_MODEL_KABYLAKE 0x8E

Kabylake Dektop.

Definition at line 234 of file ProcessorInfo.h.

◆ CPU_MODEL_KABYLAKE_DT

#define CPU_MODEL_KABYLAKE_DT 0x9E

Definition at line 237 of file ProcessorInfo.h.

◆ CPU_MODEL_KABYLAKE_ULT

#define CPU_MODEL_KABYLAKE_ULT 0x8E

Definition at line 235 of file ProcessorInfo.h.

◆ CPU_MODEL_KABYLAKE_ULX

#define CPU_MODEL_KABYLAKE_ULX 0x8E

Definition at line 236 of file ProcessorInfo.h.

◆ CPU_MODEL_MEROM

#define CPU_MODEL_MEROM 0x0F

Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom.

Definition at line 197 of file ProcessorInfo.h.

◆ CPU_MODEL_NEHALEM

#define CPU_MODEL_NEHALEM 0x1A

Bloomfield, Nehalem-EP, Nehalem-WS, Gainestown.

Definition at line 199 of file ProcessorInfo.h.

◆ CPU_MODEL_NEHALEM_EX

#define CPU_MODEL_NEHALEM_EX 0x2E

Beckton.

Definition at line 203 of file ProcessorInfo.h.

◆ CPU_MODEL_NORTHWOOD

#define CPU_MODEL_NORTHWOOD 0x02

Northwood, Prestonia, Gallatin.

Definition at line 190 of file ProcessorInfo.h.

◆ CPU_MODEL_PENRYN

#define CPU_MODEL_PENRYN 0x17

Wolfdale, Yorkfield, Harpertown, Penryn.

Definition at line 198 of file ProcessorInfo.h.

◆ CPU_MODEL_PRESCOTT

#define CPU_MODEL_PRESCOTT 0x03

Prescott, Nocona, Cranford, Potomac.

Definition at line 191 of file ProcessorInfo.h.

◆ CPU_MODEL_PRESCOTT_2M

#define CPU_MODEL_PRESCOTT_2M 0x04

Prescott 2M, Smithfield, Irwindale, Paxville.

Definition at line 192 of file ProcessorInfo.h.

◆ CPU_MODEL_RAPTORLAKE_HX

#define CPU_MODEL_RAPTORLAKE_HX 0xBF

Raptor Lake C0 stepping.

Definition at line 252 of file ProcessorInfo.h.

◆ CPU_MODEL_RAPTORLAKE_S

#define CPU_MODEL_RAPTORLAKE_S 0xB7

Raptor Lake B0 stepping.

Definition at line 251 of file ProcessorInfo.h.

◆ CPU_MODEL_ROCKETLAKE_S

#define CPU_MODEL_ROCKETLAKE_S 0xA7

desktop RocketLake

Definition at line 248 of file ProcessorInfo.h.

◆ CPU_MODEL_SALTWELL

#define CPU_MODEL_SALTWELL 0x36

Saltwell, Cedarview.

Definition at line 210 of file ProcessorInfo.h.

◆ CPU_MODEL_SANDYBRIDGE

#define CPU_MODEL_SANDYBRIDGE 0x2A

Sandy Bridge.

Definition at line 208 of file ProcessorInfo.h.

◆ CPU_MODEL_SILVERMONT

#define CPU_MODEL_SILVERMONT 0x37

Bay Trail.

Definition at line 211 of file ProcessorInfo.h.

◆ CPU_MODEL_SKYLAKE

#define CPU_MODEL_SKYLAKE 0x4E

Skylake-S.

Definition at line 225 of file ProcessorInfo.h.

◆ CPU_MODEL_SKYLAKE_DT

#define CPU_MODEL_SKYLAKE_DT 0x5E

Definition at line 228 of file ProcessorInfo.h.

◆ CPU_MODEL_SKYLAKE_ULT

#define CPU_MODEL_SKYLAKE_ULT 0x4E

Definition at line 226 of file ProcessorInfo.h.

◆ CPU_MODEL_SKYLAKE_ULX

#define CPU_MODEL_SKYLAKE_ULX 0x4E

Definition at line 227 of file ProcessorInfo.h.

◆ CPU_MODEL_SKYLAKE_W

#define CPU_MODEL_SKYLAKE_W 0x55

Definition at line 229 of file ProcessorInfo.h.

◆ CPU_MODEL_TIGERLAKE_U

#define CPU_MODEL_TIGERLAKE_U 0x8C

Definition at line 249 of file ProcessorInfo.h.

◆ CPU_MODEL_WESTMERE

#define CPU_MODEL_WESTMERE 0x2C

Gulftown, Westmere-EP, Westmere-WS.

Definition at line 206 of file ProcessorInfo.h.

◆ CPU_MODEL_WESTMERE_EX

#define CPU_MODEL_WESTMERE_EX 0x2F

Definition at line 207 of file ProcessorInfo.h.

◆ CPU_MODEL_WILLAMETTE

#define CPU_MODEL_WILLAMETTE 0x01

Willamette, Foster.

Definition at line 189 of file ProcessorInfo.h.

◆ CPU_MODEL_XEON_MILL

#define CPU_MODEL_XEON_MILL 0x85

Knights Mill.

Definition at line 233 of file ProcessorInfo.h.

◆ CPU_MODEL_YONAH

#define CPU_MODEL_YONAH 0x0E

Sossaman, Yonah.

Definition at line 196 of file ProcessorInfo.h.

◆ DEFAULT_ART_CLOCK_SOURCE

#define DEFAULT_ART_CLOCK_SOURCE CLIENT_ART_CLOCK_SOURCE

Definition at line 32 of file ProcessorInfo.h.

◆ EFI_PLATFORM_INFORMATION

#define EFI_PLATFORM_INFORMATION 0x000000CE

Definition at line 37 of file ProcessorInfo.h.

◆ ENERGY_POLICY_NORMAL

#define ENERGY_POLICY_NORMAL 6

Definition at line 77 of file ProcessorInfo.h.

◆ ENERGY_POLICY_PERFORMANCE

#define ENERGY_POLICY_PERFORMANCE 0

Definition at line 76 of file ProcessorInfo.h.

◆ ENERGY_POLICY_POWERSAVE

#define ENERGY_POLICY_POWERSAVE 15

Definition at line 78 of file ProcessorInfo.h.

◆ FLEX_RATIO_EN

#define FLEX_RATIO_EN (1U << 16U)

Definition at line 55 of file ProcessorInfo.h.

◆ FLEX_RATIO_LOCK

#define FLEX_RATIO_LOCK (1U << 20U)

Definition at line 54 of file ProcessorInfo.h.

◆ GET_PAT_N

#define GET_PAT_N	(		PatMsr,
			PatIndex )

Value:

(RShiftU64 ((PatMsr), (PatIndex) * 8) & PAT_ENTRY_BIT_MASK)

PAT_ENTRY_BIT_MASK

#define PAT_ENTRY_BIT_MASK

Definition ProcessorInfo.h:149

RShiftU64

UINT64 EFIAPI RShiftU64(IN UINT64 Operand, IN UINTN Count)

Definition UserMath.c:86

Definition at line 164 of file ProcessorInfo.h.

◆ IRTL_1024_NS

#define IRTL_1024_NS (2 << 10)

Definition at line 96 of file ProcessorInfo.h.

◆ IRTL_1048576_NS

#define IRTL_1048576_NS (4 << 10)

Definition at line 98 of file ProcessorInfo.h.

◆ IRTL_1_NS

#define IRTL_1_NS (0 << 10)

Definition at line 94 of file ProcessorInfo.h.

◆ IRTL_32768_NS

#define IRTL_32768_NS (3 << 10)

Definition at line 97 of file ProcessorInfo.h.

◆ IRTL_32_NS

#define IRTL_32_NS (1 << 10)

Definition at line 95 of file ProcessorInfo.h.

◆ IRTL_33554432_NS

#define IRTL_33554432_NS (5 << 10)

Definition at line 99 of file ProcessorInfo.h.

◆ IRTL_RESPONSE_MASK

#define IRTL_RESPONSE_MASK (0x3ff)

Definition at line 100 of file ProcessorInfo.h.

◆ IRTL_VALID

#define IRTL_VALID (1 << 15)

Definition at line 93 of file ProcessorInfo.h.

◆ K10_COFVID_STATUS

#define K10_COFVID_STATUS 0xC0010071

Definition at line 186 of file ProcessorInfo.h.

◆ K10_PSTATE_STATUS

#define K10_PSTATE_STATUS 0xC0010064

Definition at line 187 of file ProcessorInfo.h.

◆ K8_FIDVID_STATUS

#define K8_FIDVID_STATUS 0xC0010042

Definition at line 185 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_1C_OFFSET

#define MAX_RATIO_LIMIT_1C_OFFSET 0

Definition at line 73 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_2C_OFFSET

#define MAX_RATIO_LIMIT_2C_OFFSET 8

Definition at line 72 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_3C_OFFSET

#define MAX_RATIO_LIMIT_3C_OFFSET 16

Definition at line 71 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_4C_OFFSET

#define MAX_RATIO_LIMIT_4C_OFFSET 24

Definition at line 70 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_5C_OFFSET

#define MAX_RATIO_LIMIT_5C_OFFSET 32

Definition at line 69 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_6C_OFFSET

#define MAX_RATIO_LIMIT_6C_OFFSET 40

Definition at line 68 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_7C_OFFSET

#define MAX_RATIO_LIMIT_7C_OFFSET 48

Definition at line 67 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_8C_OFFSET

#define MAX_RATIO_LIMIT_8C_OFFSET 56

Definition at line 66 of file ProcessorInfo.h.

◆ MAX_RATIO_LIMIT_MASK

#define MAX_RATIO_LIMIT_MASK 0xff

Definition at line 74 of file ProcessorInfo.h.

◆ MISC_PWR_MGMT_EIST_HW_DIS

#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)

Definition at line 64 of file ProcessorInfo.h.

◆ MISC_PWR_MGMT_LOCK

#define MISC_PWR_MGMT_LOCK (1 << 13)

Definition at line 65 of file ProcessorInfo.h.

◆ MODIFY_PAT_MSR

#define MODIFY_PAT_MSR	(	PatMsr,
		PatIndex,
		PatType )

Value:

(((PatMsr) & ~SET_PAT_N ((PatIndex), PAT_ENTRY_BIT_MASK)) | SET_PAT_N ((PatIndex), (PatType)))

SET_PAT_N

#define SET_PAT_N(PatIndex, PatType)

Definition ProcessorInfo.h:159

Definition at line 169 of file ProcessorInfo.h.

◆ MSR_CORE_THREAD_COUNT

#define MSR_CORE_THREAD_COUNT 0x35

Definition at line 35 of file ProcessorInfo.h.

◆ MSR_DRAM_ENERGY_STATUS

#define MSR_DRAM_ENERGY_STATUS 0x619

Definition at line 127 of file ProcessorInfo.h.

◆ MSR_DRAM_PERF_STATUS

#define MSR_DRAM_PERF_STATUS 0x61B

Definition at line 128 of file ProcessorInfo.h.

◆ MSR_DRAM_POWER_INFO

#define MSR_DRAM_POWER_INFO 0x61C

Definition at line 129 of file ProcessorInfo.h.

◆ MSR_DRAM_POWER_LIMIT

#define MSR_DRAM_POWER_LIMIT 0x618

Definition at line 126 of file ProcessorInfo.h.

◆ MSR_FEATURE_CONFIG

#define MSR_FEATURE_CONFIG 0x13C

Definition at line 52 of file ProcessorInfo.h.

◆ MSR_FLEX_RATIO

#define MSR_FLEX_RATIO 0x194

Definition at line 53 of file ProcessorInfo.h.

◆ MSR_IA32_CR_PAT

#define MSR_IA32_CR_PAT 0x277

Definition at line 81 of file ProcessorInfo.h.

◆ MSR_IA32_ENERGY_PERFORMANCE_BIAS

#define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1B0

Definition at line 75 of file ProcessorInfo.h.

◆ MSR_IA32_EXT_CONFIG

#define MSR_IA32_EXT_CONFIG 0xEE

Definition at line 51 of file ProcessorInfo.h.

◆ MSR_IA32_PERF_CONTROL

#define MSR_IA32_PERF_CONTROL 0x199

Definition at line 56 of file ProcessorInfo.h.

◆ MSR_LT_LOCK_MEMORY

#define MSR_LT_LOCK_MEMORY 0x2E7

Definition at line 80 of file ProcessorInfo.h.

◆ MSR_MISC_PWR_MGMT

#define MSR_MISC_PWR_MGMT 0x1AA

Definition at line 63 of file ProcessorInfo.h.

◆ MSR_PIC_MSG_CONTROL

#define MSR_PIC_MSG_CONTROL 0x2E

Definition at line 34 of file ProcessorInfo.h.

◆ MSR_PKG_ENERGY_STATUS

#define MSR_PKG_ENERGY_STATUS 0x611

Definition at line 110 of file ProcessorInfo.h.

◆ MSR_PKG_PERF_STATUS

#define MSR_PKG_PERF_STATUS 0x613

Definition at line 111 of file ProcessorInfo.h.

◆ MSR_PKG_POWER_LIMIT

#define MSR_PKG_POWER_LIMIT 0x610

Definition at line 103 of file ProcessorInfo.h.

◆ MSR_PKG_POWER_SKU

#define MSR_PKG_POWER_SKU 0x614

Definition at line 112 of file ProcessorInfo.h.

◆ MSR_PKG_POWER_SKU_UNIT

#define MSR_PKG_POWER_SKU_UNIT 0x606

Definition at line 88 of file ProcessorInfo.h.

◆ MSR_PKGC3_IRTL

#define MSR_PKGC3_IRTL 0x60A

Definition at line 90 of file ProcessorInfo.h.

◆ MSR_PKGC6_IRTL

#define MSR_PKGC6_IRTL 0x60B

Definition at line 91 of file ProcessorInfo.h.

◆ MSR_PKGC7_IRTL

#define MSR_PKGC7_IRTL 0x60C

Definition at line 92 of file ProcessorInfo.h.

◆ MSR_PMG_IO_CAPTURE_BASE

#define MSR_PMG_IO_CAPTURE_BASE 0xE4

Definition at line 50 of file ProcessorInfo.h.

◆ MSR_POWER_CTL

#define MSR_POWER_CTL 0x1FC

Definition at line 79 of file ProcessorInfo.h.

◆ MSR_PP0_CURRENT_CONFIG

#define MSR_PP0_CURRENT_CONFIG 0x601

Definition at line 84 of file ProcessorInfo.h.

◆ MSR_PP0_ENERGY_STATUS

#define MSR_PP0_ENERGY_STATUS 0x639

Definition at line 116 of file ProcessorInfo.h.

◆ MSR_PP0_PERF_STATUS

#define MSR_PP0_PERF_STATUS 0x63B

Definition at line 118 of file ProcessorInfo.h.

◆ MSR_PP0_POLICY

#define MSR_PP0_POLICY 0x63A

Definition at line 117 of file ProcessorInfo.h.

◆ MSR_PP0_POWER_LIMIT

#define MSR_PP0_POWER_LIMIT 0x638

Definition at line 115 of file ProcessorInfo.h.

◆ MSR_PP1_CURRENT_CONFIG

#define MSR_PP1_CURRENT_CONFIG 0x602

Definition at line 86 of file ProcessorInfo.h.

◆ MSR_PP1_ENERGY_STATUS

#define MSR_PP1_ENERGY_STATUS 0x641

Definition at line 122 of file ProcessorInfo.h.

◆ MSR_PP1_POLICY

#define MSR_PP1_POLICY 0x642

Definition at line 123 of file ProcessorInfo.h.

◆ MSR_PP1_POWER_LIMIT

#define MSR_PP1_POWER_LIMIT 0x640

Definition at line 121 of file ProcessorInfo.h.

◆ MSR_TEMPERATURE_TARGET

#define MSR_TEMPERATURE_TARGET 0x1A2

Definition at line 62 of file ProcessorInfo.h.

◆ MSR_THERM2_CTL

#define MSR_THERM2_CTL 0x19D

Definition at line 57 of file ProcessorInfo.h.

◆ N_EFI_PLATFORM_INFO_MAX_RATIO

#define N_EFI_PLATFORM_INFO_MAX_RATIO 8

Definition at line 40 of file ProcessorInfo.h.

◆ N_EFI_PLATFORM_INFO_MIN_RATIO

#define N_EFI_PLATFORM_INFO_MIN_RATIO 40

Definition at line 38 of file ProcessorInfo.h.

◆ N_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET

#define N_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30

Definition at line 45 of file ProcessorInfo.h.

◆ N_EFI_PLATFORM_INFO_RATIO_LIMIT

#define N_EFI_PLATFORM_INFO_RATIO_LIMIT 28

Definition at line 42 of file ProcessorInfo.h.

◆ PAT_DEFAULTS

#define PAT_DEFAULTS

Value:

  (             \
  SET_PAT_N (0, PatWriteBack)     | \
  SET_PAT_N (1, PatWriteThrough)  | \
  SET_PAT_N (2, PatUncached)      | \
  SET_PAT_N (3, PatUncacheable)   | \
  SET_PAT_N (4, PatWriteBack)     | \
  SET_PAT_N (5, PatWriteThrough)  | \
  SET_PAT_N (6, PatUncached)      | \
  SET_PAT_N (7, PatUncacheable)     \
)

Definition at line 174 of file ProcessorInfo.h.

◆ PAT_ENTRY_BIT_MASK

#define PAT_ENTRY_BIT_MASK (0xFFU)

Definition at line 149 of file ProcessorInfo.h.

◆ PAT_INDEX_MAX

#define PAT_INDEX_MAX 8

Definition at line 154 of file ProcessorInfo.h.

◆ PKG_POWER_LIMIT_CLAMP

#define PKG_POWER_LIMIT_CLAMP (1 << 16)

Definition at line 106 of file ProcessorInfo.h.

◆ PKG_POWER_LIMIT_EN

#define PKG_POWER_LIMIT_EN (1 << 15)

Definition at line 105 of file ProcessorInfo.h.

◆ PKG_POWER_LIMIT_MASK

#define PKG_POWER_LIMIT_MASK 0x7fff

Definition at line 104 of file ProcessorInfo.h.

◆ PKG_POWER_LIMIT_TIME_MASK

#define PKG_POWER_LIMIT_TIME_MASK 0x7f

Definition at line 108 of file ProcessorInfo.h.

◆ PKG_POWER_LIMIT_TIME_SHIFT

#define PKG_POWER_LIMIT_TIME_SHIFT 17

Definition at line 107 of file ProcessorInfo.h.

◆ PP0_CURRENT_LIMIT

#define PP0_CURRENT_LIMIT (112 << 3)

112 A

Definition at line 85 of file ProcessorInfo.h.

◆ PP1_CURRENT_LIMIT

#define PP1_CURRENT_LIMIT (35 << 3)

35 A

Definition at line 87 of file ProcessorInfo.h.

◆ SERVER_ART_CLOCK_SOURCE

#define SERVER_ART_CLOCK_SOURCE 25000000ULL

Definition at line 29 of file ProcessorInfo.h.

◆ SET_PAT_N

#define SET_PAT_N	(		PatIndex,
			PatType )

Value:

(LShiftU64 ((PatType) * 1ULL, (PatIndex) * 8))

LShiftU64

UINT64 EFIAPI LShiftU64(IN UINT64 Operand, IN UINTN Count)

Definition UserMath.c:76

Definition at line 159 of file ProcessorInfo.h.

◆ TURBO_DISABLE_MASK

#define TURBO_DISABLE_MASK ((UINT64)1 << 38)

Definition at line 59 of file ProcessorInfo.h.

◆ TURBO_MODE_DISABLE_BIT

#define TURBO_MODE_DISABLE_BIT 38

Definition at line 60 of file ProcessorInfo.h.

Enumeration Type Documentation

◆ CPU_P_STATE_COORDINATION

enum CPU_P_STATE_COORDINATION

P-State Coordination.

Enumerator
CpuPStateCoordinationSoftwareAll	The OS Power Manager is responsible for coordinating the P-state among logical processors with dependencies and must initiate the transition on all of those Logical Processors.
CpuPStateCoordinationSoftwareAny	The OS Power Manager is responsible for coordinating the P-state among logical processors with dependencies and may initiate the transition on any of those Logical Processors.
CpuPStateCoordinationHardwareAll	The processor hardware is responsible for coordinating the P-state among logical processors dependencies. The OS is responsible for keeping the P-state request up to date on all logical processors.

Definition at line 268 of file ProcessorInfo.h.

◆ PAT_MEMORY_CACHE_TYPE

enum PAT_MEMORY_CACHE_TYPE

Enumerator
PatUncacheable
PatWriteCombining	Special hardware burst mode (not L1-L3) intended for graphics memory (ref. 11.3.1).
PatWriteThrough
PatWriteProtected
PatWriteBack
PatUncached

Definition at line 137 of file ProcessorInfo.h.

Macros

Enumerations

Detailed Description

Macro Definition Documentation

◆ AMD_CPU_EXT_FAMILY_0FH

◆ AMD_CPU_EXT_FAMILY_10H

◆ AMD_CPU_EXT_FAMILY_15H

◆ AMD_CPU_EXT_FAMILY_16H

◆ AMD_CPU_EXT_FAMILY_17H

◆ AMD_CPU_EXT_FAMILY_19H

◆ AMD_CPU_EXT_FAMILY_1AH

◆ AMD_CPU_FAMILY

◆ ATOM_ART_CLOCK_SOURCE

◆ B_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET

◆ B_EFI_PLATFORM_INFO_RATIO_LIMIT

◆ B_EFI_PLATFORM_INFO_RATIO_MASK

◆ B_EFI_PLATFORM_INFO_SMM_SAVE_CONTROL

◆ B_EFI_PLATFORM_INFO_TDC_TDP_LIMIT

◆ BASE_NHM_CLOCK_SOURCE

◆ BRIDGE_BCLK

◆ CLIENT_ART_CLOCK_SOURCE

◆ CPU_MODEL_AIRMONT

◆ CPU_MODEL_ALDERLAKE_S

◆ CPU_MODEL_ARROWLAKE_HX

◆ CPU_MODEL_ARROWLAKE_S

◆ CPU_MODEL_ARROWLAKE_U

◆ CPU_MODEL_AVOTON

◆ CPU_MODEL_BANIAS

◆ CPU_MODEL_BONNELL

◆ CPU_MODEL_BONNELL_MID

◆ CPU_MODEL_BROADWELL

◆ CPU_MODEL_BROADWELL_EP

◆ CPU_MODEL_BROADWELL_ULT

◆ CPU_MODEL_BROADWELL_ULX

◆ CPU_MODEL_BRYSTALWELL

◆ CPU_MODEL_CANNONLAKE

◆ CPU_MODEL_CEDAR_MILL

◆ CPU_MODEL_COFFEELAKE

◆ CPU_MODEL_COFFEELAKE_DT

◆ CPU_MODEL_COFFEELAKE_ULT

◆ CPU_MODEL_COFFEELAKE_ULX

◆ CPU_MODEL_COMETLAKE_S

◆ CPU_MODEL_COMETLAKE_U

◆ CPU_MODEL_COMETLAKE_Y

◆ CPU_MODEL_CRYSTALWELL

◆ CPU_MODEL_DALES

◆ CPU_MODEL_DALES_32NM

◆ CPU_MODEL_DENVERTON

◆ CPU_MODEL_DOTHAN

◆ CPU_MODEL_FIELDS

◆ CPU_MODEL_GOLDMONT

◆ CPU_MODEL_HASWELL

◆ CPU_MODEL_HASWELL_EP

◆ CPU_MODEL_HASWELL_ULT

◆ CPU_MODEL_ICELAKE_SP

◆ CPU_MODEL_ICELAKE_U

◆ CPU_MODEL_ICELAKE_Y

◆ CPU_MODEL_IVYBRIDGE

◆ CPU_MODEL_IVYBRIDGE_EP

◆ CPU_MODEL_JAKETOWN

◆ CPU_MODEL_KABYLAKE

◆ CPU_MODEL_KABYLAKE_DT

◆ CPU_MODEL_KABYLAKE_ULT

◆ CPU_MODEL_KABYLAKE_ULX

◆ CPU_MODEL_MEROM

◆ CPU_MODEL_NEHALEM

◆ CPU_MODEL_NEHALEM_EX

◆ CPU_MODEL_NORTHWOOD

◆ CPU_MODEL_PENRYN

◆ CPU_MODEL_PRESCOTT

◆ CPU_MODEL_PRESCOTT_2M

◆ CPU_MODEL_RAPTORLAKE_HX

◆ CPU_MODEL_RAPTORLAKE_S

◆ CPU_MODEL_ROCKETLAKE_S

◆ CPU_MODEL_SALTWELL

◆ CPU_MODEL_SANDYBRIDGE

◆ CPU_MODEL_SILVERMONT

◆ CPU_MODEL_SKYLAKE

◆ CPU_MODEL_SKYLAKE_DT

◆ CPU_MODEL_SKYLAKE_ULT