CpuId.h File Reference

#include <Register/Cpuid.h>

Go to the source code of this file.

Macros
#define	CPUID_L2_CACHE_FEATURE   0x80000006
#define	CPUID_FEATURE_FPU   BIT0
	Floating point unit on-chip.
#define	CPUID_FEATURE_VME   BIT1
	Virtual Mode Extension.
#define	CPUID_FEATURE_DE   BIT2
	Debugging Extension.
#define	CPUID_FEATURE_PSE   BIT3
	Page Size Extension.
#define	CPUID_FEATURE_TSC   BIT4
	Time Stamp Counter.
#define	CPUID_FEATURE_MSR   BIT5
	Model Specific Registers.
#define	CPUID_FEATURE_PAE   BIT6
	Physical Address Extension.
#define	CPUID_FEATURE_MCE   BIT7
	Machine Check Exception.
#define	CPUID_FEATURE_CX8   BIT8
	CMPXCHG8B.
#define	CPUID_FEATURE_APIC   BIT9
	On-chip APIC.
#define	CPUID_FEATURE_SEP   BIT11
	Fast System Call.
#define	CPUID_FEATURE_MTRR   BIT12
	Memory Type Range Register.
#define	CPUID_FEATURE_PGE   BIT13
	Page Global Enable.
#define	CPUID_FEATURE_MCA   BIT14
	Machine Check Architecture.
#define	CPUID_FEATURE_CMOV   BIT15
	Conditional Move Instruction.
#define	CPUID_FEATURE_PAT   BIT16
	Page Attribute Table.
#define	CPUID_FEATURE_PSE36   BIT17
	36-bit Page Size Extension
#define	CPUID_FEATURE_PSN   BIT18
	Processor Serial Number.
#define	CPUID_FEATURE_CLFSH   BIT19
	CLFLUSH Instruction Supported.
#define	CPUID_FEATURE_RESV20   BIT20
	Reserved.
#define	CPUID_FEATURE_DS   BIT21
	Debug Store.
#define	CPUID_FEATURE_ACPI   BIT22
	Thermal Monitor and Clock Control.
#define	CPUID_FEATURE_MMX   BIT23
	MMX Supported.
#define	CPUID_FEATURE_FXSR   BIT24
	Fast Floating Point Save/Restore.
#define	CPUID_FEATURE_SSE   BIT25
	Streaming SIMD Extensions.
#define	CPUID_FEATURE_SSE2   BIT26
	Streaming SIMD Extensions 2.
#define	CPUID_FEATURE_SS   BIT27
	Self-Snoop.
#define	CPUID_FEATURE_HTT   BIT28
	Hyper-Threading Technology.
#define	CPUID_FEATURE_TM   BIT29
	Thermal Monitor (TM1)
#define	CPUID_FEATURE_IA64   BIT30
	Itanium Family Emulating IA-32.
#define	CPUID_FEATURE_PBE   BIT31
	Pending Break Enable.
#define	CPUID_FEATURE_SSE3   BIT32
	Streaming SIMD extensions 3.
#define	CPUID_FEATURE_PCLMULQDQ   BIT33
	PCLMULQDQ Instruction.
#define	CPUID_FEATURE_DTES64   BIT34
	64-Bit Debug Store
#define	CPUID_FEATURE_MONITOR   BIT35
	MONITOR/MWAIT.
#define	CPUID_FEATURE_DSCPL   BIT36
	CPL Qualified Debug Store.
#define	CPUID_FEATURE_VMX   BIT37
	Virtual Machine Extensions (VMX)
#define	CPUID_FEATURE_SMX   BIT38
	Safer Mode Extensions (SMX)
#define	CPUID_FEATURE_EST   BIT39
	Enhanced Intel SpeedStep (GV3)
#define	CPUID_FEATURE_TM2   BIT40
	Thermal Monitor 2.
#define	CPUID_FEATURE_SSSE3   BIT41
	Supplemental SSE3 Instructions.
#define	CPUID_FEATURE_CID   BIT42
	L1 Context ID.
#define	CPUID_FEATURE_SEGLIM64   BIT43
	64-bit segment limit checking
#define	CPUID_FEATURE_RESVH12   BIT44
	Reserved.
#define	CPUID_FEATURE_CX16   BIT45
	CMPXCHG16B Instruction.
#define	CPUID_FEATURE_xTPR   BIT46
	Task Priority Update Control.
#define	CPUID_FEATURE_PDCM   BIT47
	Perfmon/Debug Capability MSR.
#define	CPUID_FEATURE_RESVH16   BIT48
	Reserved.
#define	CPUID_FEATURE_PCID   BIT49
	ASID-PCID support.
#define	CPUID_FEATURE_DCA   BIT50
	Direct Cache Access.
#define	CPUID_FEATURE_SSE4_1   BIT51
	Streaming SIMD Extensions 4.1.
#define	CPUID_FEATURE_SSE4_2   BIT52
	Streaming SIMD Extensions 4.1.
#define	CPUID_FEATURE_xAPIC   BIT53
	Extended xAPIC Support.
#define	CPUID_FEATURE_MOVBE   BIT54
	MOVBE Instruction.
#define	CPUID_FEATURE_POPCNT   BIT55
	POPCNT Instruction.
#define	CPUID_FEATURE_TSCTMR   BIT56
	TSC deadline timer.
#define	CPUID_FEATURE_AES   BIT57
	AES instructions.
#define	CPUID_FEATURE_XSAVE   BIT58
	XSAVE/XSTOR States.
#define	CPUID_FEATURE_OSXSAVE   BIT59
	OS Has Enabled XSETBV/XGETBV.
#define	CPUID_FEATURE_AVX1_0   BIT60
	AVX 1.0 instructions.
#define	CPUID_FEATURE_RDRAND   BIT61
	RDRAND instruction.
#define	CPUID_FEATURE_F16C   BIT62
	Float16 convert instructions.
#define	CPUID_FEATURE_VMM   BIT63
	VMM (Hypervisor) present.
#define	CPUID_EXTFEATURE_SYSCALL   BIT11
	SYSCALL/sysret.
#define	CPUID_EXTFEATURE_XD   BIT20
	eXecute Disable
#define	CPUID_EXTFEATURE_1GBPAGE   BIT21
	1GB pages
#define	CPUID_EXTFEATURE_RDTSCP   BIT27
	RDTSCP.
#define	CPUID_EXTFEATURE_EM64T   BIT29
	Extended Mem 64 Technology.
#define	CPUID_EXTFEATURE_LAHF   BIT32
	LAFH/SAHF instructions.
#define	CPUID_EXTFEATURE_TSCI   BIT8
	TSC Invariant.
#define	CPUID_CACHE_SIZE   16
	Number of 8-bit descriptor values.
#define	CPUID_VENDOR_INTEL   0x756E6547
#define	CPUID_VENDOR_AMD   0x68747541

Enumerations
enum	{   CpuIdCacheNull = 0x00 , CpuIdCacheItlb4K_32_4 = 0x01 , CpuIdCacheItlb4M_2 = 0x02 , CpuIdCacheDtlb4K_64_4 = 0x03 ,   CpuIdCacheDtlb4M_8_4 = 0x04 , CpuIdCacheDtlb4M_32_4 = 0x05 , CpuIdCacheL1I_8K = 0x06 , CpuIdCacheL1I_16K = 0x08 ,   CpuIdCacheL1I_32K = 0x09 , CpuIdCacheL1D_8K = 0x0A , CpuIdCacheL1D_16K = 0x0C , CpuIdCacheL1D_16K_4_32 = 0x0D ,   CpuIdCacheL2_256K_8_64 = 0x21 , CpuIdCacheL3_512K = 0x22 , CpuIdCacheL3_1M = 0x23 , CpuIdCacheL3_2M = 0x25 ,   CpuIdCacheL3_4M = 0x29 , CpuIdCacheL1D_32K_8 = 0x2C , CpuIdCacheL1I_32K_8 = 0x30 , CpuIdCacheL2_128K_S4 = 0x39 ,   CpuIdCacheL2_192K_S6 = 0x3A , CpuIdCacheL2_128K_S2 = 0x3B , CpuIdCacheL2_256K_S4 = 0x3C , CpuIdCacheL2_384K_S6 = 0x3D ,   CpuIdCacheL2_512K_S4 = 0x3E , CpuIdCacheNoCache = 0x40 , CpuIdCacheL2_128K = 0x41 , CpuIdCacheL2_256K = 0x42 ,   CpuIdCacheL2_512K = 0x43 , CpuIdCacheL2_1M_4 = 0x44 , CpuIdCacheL2_2M_4 = 0x45 , CpuIdCacheL3_4M_4_64 = 0x46 ,   CpuIdCacheL3_8M_8_64 = 0x47 , CpuIdCacheL2_3M_12_64 = 0x48 , CpuIdCacheL2_4M_16_64 = 0x49 , CpuIdCacheL2_6M_12_64 = 0x4A ,   CpuIdCacheL2_8M_16_64 = 0x4B , CpuIdCacheL2_12M_12_64 = 0x4C , CpuIdCacheL2_16M_16_64 = 0x4D , CpuIdCacheL2_6M_24_64 = 0x4E ,   CpuIdCacheItlb64 = 0x50 , CpuIdCacheItlb128 = 0x51 , CpuIdCacheItlb256 = 0x52 , CpuIdCacheItlb4M2M_7 = 0x55 ,   CpuIdCacheDtlb4M_16_4 = 0x56 , CpuIdCacheDtlb4K_16_4 = 0x57 , CpuIdCacheDtlb4M2M_32_4 = 0x5A , CpuIdCacheDtlb64 = 0x5B ,   CpuIdCacheDtlb128 = 0x5C , CpuIdCacheDtlb256 = 0x5D , CpuIdCacheL1D_16K_8_64 = 0x60 , CpuIdCacheL1D_8K_4_64 = 0x66 ,   CpuIdCacheL1D_16K_4_64 = 0x67 , CpuIdCacheL1D_32K_4_64 = 0x68 , CpuIdCacheTRACE_12K_8 = 0x70 , CpuIdCacheTRACE_16K_8 = 0x71 ,   CpuIdCacheTRACE_32K_8 = 0x72 , CpuIdCacheTRACE_64K_8 = 0x73 , CpuIdCacheL2_1M_4_64 = 0x78 , CpuIdCacheL2_128K_8_64_2 = 0x79 ,   CpuIdCacheL2_256K_8_64_2 = 0x7A , CpuIdCacheL2_512K_8_64_2 = 0x7B , CpuIdCacheL2_1M_8_64_2 = 0x7C , CpuIdCacheL2_2M_8_64 = 0x7D ,   CpuIdCacheL2_512K_2_64 = 0x7F , CpuIdCacheL2_256K_8_32 = 0x82 , CpuIdCacheL2_512K_8_32 = 0x83 , CpuIdCacheL2_1M_8_32 = 0x84 ,   CpuIdCacheL2_2M_8_32 = 0x85 , CpuIdCacheL2_512K_4_64 = 0x86 , CpuIdCacheL2_1M_8_64 = 0x87 , CpuIdCacheItlb4K_128_4 = 0xB0 ,   CpuIdCacheItlb4M_4_4 = 0xB1 , CpuIdCacheItlb2M_8_4 = 0xB1 , CpuIdCacheItlb4M_8 = 0xB1 , CpuIdCacheItlb4K_64_4 = 0xB2 ,   CpuIdCacheDtlb4K_128_4 = 0xB3 , CpuIdCacheDtlb4K_256_4 = 0xB4 , CpuIdCache2TLB_4K_512_4 = 0xCA , CpuIdCacheL3_512K_4_64 = 0xD0 ,   CpuIdCacheL3_1M_4_64 = 0xD1 , CpuIdCacheL3_2M_4_64 = 0xD2 , CpuIdCacheL3_1M_8_64 = 0xD6 , CpuIdCacheL3_2M_8_64 = 0xD7 ,   CpuIdCacheL3_4M_8_64 = 0xD8 , CpuIdCacheL3_1M5_12_64 = 0xDC , CpuIdCacheL3_3M_12_64 = 0xDD , CpuIdCacheL3_6M_12_64 = 0xDE ,   CpuIdCacheL3_2M_16_64 = 0xE2 , CpuIdCacheL3_4M_16_64 = 0xE3 , CpuIdCacheL3_8M_16_64 = 0xE4 , CpuIdCachePrefetch64 = 0xF0 ,   CpuIdCachePrefetch128 = 0xF1 }

Detailed Description

Copyright (C) 2016, The HermitCrabs Lab. All rights reserved.

All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file CpuId.h.

Macro Definition Documentation

CPUID_CACHE_SIZE

#define CPUID_CACHE_SIZE   16

Number of 8-bit descriptor values.

Definition at line 116 of file CpuId.h.

CPUID_EXTFEATURE_1GBPAGE

#define CPUID_EXTFEATURE_1GBPAGE   BIT21

1GB pages

Definition at line 97 of file CpuId.h.

CPUID_EXTFEATURE_EM64T

#define CPUID_EXTFEATURE_EM64T   BIT29

Extended Mem 64 Technology.

Definition at line 101 of file CpuId.h.

CPUID_EXTFEATURE_LAHF

#define CPUID_EXTFEATURE_LAHF   BIT32

LAFH/SAHF instructions.

Definition at line 103 of file CpuId.h.

CPUID_EXTFEATURE_RDTSCP

#define CPUID_EXTFEATURE_RDTSCP   BIT27

RDTSCP.

Definition at line 99 of file CpuId.h.

CPUID_EXTFEATURE_SYSCALL

#define CPUID_EXTFEATURE_SYSCALL   BIT11

SYSCALL/sysret.

Definition at line 94 of file CpuId.h.

CPUID_EXTFEATURE_TSCI

#define CPUID_EXTFEATURE_TSCI   BIT8

TSC Invariant.

Definition at line 108 of file CpuId.h.

CPUID_EXTFEATURE_XD

#define CPUID_EXTFEATURE_XD   BIT20

eXecute Disable

Definition at line 96 of file CpuId.h.

CPUID_FEATURE_ACPI

#define CPUID_FEATURE_ACPI   BIT22

Thermal Monitor and Clock Control.

Definition at line 45 of file CpuId.h.

CPUID_FEATURE_AES

#define CPUID_FEATURE_AES   BIT57

AES instructions.

Definition at line 83 of file CpuId.h.

CPUID_FEATURE_APIC

#define CPUID_FEATURE_APIC   BIT9

On-chip APIC.

Definition at line 33 of file CpuId.h.

CPUID_FEATURE_AVX1_0

#define CPUID_FEATURE_AVX1_0   BIT60

AVX 1.0 instructions.

Definition at line 86 of file CpuId.h.

CPUID_FEATURE_CID

#define CPUID_FEATURE_CID   BIT42

L1 Context ID.

Definition at line 68 of file CpuId.h.

CPUID_FEATURE_CLFSH

#define CPUID_FEATURE_CLFSH   BIT19

CLFLUSH Instruction Supported.

Definition at line 42 of file CpuId.h.

CPUID_FEATURE_CMOV

#define CPUID_FEATURE_CMOV   BIT15

Conditional Move Instruction.

Definition at line 38 of file CpuId.h.

CPUID_FEATURE_CX16

#define CPUID_FEATURE_CX16   BIT45

CMPXCHG16B Instruction.

Definition at line 71 of file CpuId.h.

CPUID_FEATURE_CX8

#define CPUID_FEATURE_CX8   BIT8

CMPXCHG8B.

Definition at line 32 of file CpuId.h.

CPUID_FEATURE_DCA

#define CPUID_FEATURE_DCA   BIT50

Direct Cache Access.

Definition at line 76 of file CpuId.h.

CPUID_FEATURE_DE

#define CPUID_FEATURE_DE   BIT2

Debugging Extension.

Definition at line 26 of file CpuId.h.

CPUID_FEATURE_DS

#define CPUID_FEATURE_DS   BIT21

Debug Store.

Definition at line 44 of file CpuId.h.

CPUID_FEATURE_DSCPL

#define CPUID_FEATURE_DSCPL   BIT36

CPL Qualified Debug Store.

Definition at line 62 of file CpuId.h.

CPUID_FEATURE_DTES64

#define CPUID_FEATURE_DTES64   BIT34

64-Bit Debug Store

Definition at line 60 of file CpuId.h.

CPUID_FEATURE_EST

#define CPUID_FEATURE_EST   BIT39

Enhanced Intel SpeedStep (GV3)

Definition at line 65 of file CpuId.h.

CPUID_FEATURE_F16C

#define CPUID_FEATURE_F16C   BIT62

Float16 convert instructions.

Definition at line 88 of file CpuId.h.

CPUID_FEATURE_FPU

#define CPUID_FEATURE_FPU   BIT0

Floating point unit on-chip.

Definition at line 24 of file CpuId.h.

CPUID_FEATURE_FXSR

#define CPUID_FEATURE_FXSR   BIT24

Fast Floating Point Save/Restore.

Definition at line 47 of file CpuId.h.

CPUID_FEATURE_HTT

#define CPUID_FEATURE_HTT   BIT28

Hyper-Threading Technology.

Definition at line 51 of file CpuId.h.

CPUID_FEATURE_IA64

#define CPUID_FEATURE_IA64   BIT30

Itanium Family Emulating IA-32.

Definition at line 53 of file CpuId.h.

CPUID_FEATURE_MCA

#define CPUID_FEATURE_MCA   BIT14

Machine Check Architecture.

Definition at line 37 of file CpuId.h.

CPUID_FEATURE_MCE

#define CPUID_FEATURE_MCE   BIT7

Machine Check Exception.

Definition at line 31 of file CpuId.h.

CPUID_FEATURE_MMX

#define CPUID_FEATURE_MMX   BIT23

MMX Supported.

Definition at line 46 of file CpuId.h.

CPUID_FEATURE_MONITOR

#define CPUID_FEATURE_MONITOR   BIT35

MONITOR/MWAIT.

Definition at line 61 of file CpuId.h.

CPUID_FEATURE_MOVBE

#define CPUID_FEATURE_MOVBE   BIT54

MOVBE Instruction.

Definition at line 80 of file CpuId.h.

CPUID_FEATURE_MSR

#define CPUID_FEATURE_MSR   BIT5

Model Specific Registers.

Definition at line 29 of file CpuId.h.

CPUID_FEATURE_MTRR

#define CPUID_FEATURE_MTRR   BIT12

Memory Type Range Register.

Definition at line 35 of file CpuId.h.

CPUID_FEATURE_OSXSAVE

#define CPUID_FEATURE_OSXSAVE   BIT59

OS Has Enabled XSETBV/XGETBV.

Definition at line 85 of file CpuId.h.

CPUID_FEATURE_PAE

#define CPUID_FEATURE_PAE   BIT6

Physical Address Extension.

Definition at line 30 of file CpuId.h.

CPUID_FEATURE_PAT

#define CPUID_FEATURE_PAT   BIT16

Page Attribute Table.

Definition at line 39 of file CpuId.h.

CPUID_FEATURE_PBE

#define CPUID_FEATURE_PBE   BIT31

Pending Break Enable.

Definition at line 54 of file CpuId.h.

CPUID_FEATURE_PCID

#define CPUID_FEATURE_PCID   BIT49

ASID-PCID support.

Definition at line 75 of file CpuId.h.

CPUID_FEATURE_PCLMULQDQ

#define CPUID_FEATURE_PCLMULQDQ   BIT33

PCLMULQDQ Instruction.

Definition at line 59 of file CpuId.h.

CPUID_FEATURE_PDCM

#define CPUID_FEATURE_PDCM   BIT47

Perfmon/Debug Capability MSR.

Definition at line 73 of file CpuId.h.

CPUID_FEATURE_PGE

#define CPUID_FEATURE_PGE   BIT13

Page Global Enable.

Definition at line 36 of file CpuId.h.

CPUID_FEATURE_POPCNT

#define CPUID_FEATURE_POPCNT   BIT55

POPCNT Instruction.

Definition at line 81 of file CpuId.h.

CPUID_FEATURE_PSE

#define CPUID_FEATURE_PSE   BIT3

Page Size Extension.

Definition at line 27 of file CpuId.h.

CPUID_FEATURE_PSE36

#define CPUID_FEATURE_PSE36   BIT17

36-bit Page Size Extension

Definition at line 40 of file CpuId.h.

CPUID_FEATURE_PSN

#define CPUID_FEATURE_PSN   BIT18

Processor Serial Number.

Definition at line 41 of file CpuId.h.

CPUID_FEATURE_RDRAND

#define CPUID_FEATURE_RDRAND   BIT61

RDRAND instruction.

Definition at line 87 of file CpuId.h.

CPUID_FEATURE_RESV20

#define CPUID_FEATURE_RESV20   BIT20

Reserved.

Definition at line 43 of file CpuId.h.

CPUID_FEATURE_RESVH12

#define CPUID_FEATURE_RESVH12   BIT44

Reserved.

Definition at line 70 of file CpuId.h.

CPUID_FEATURE_RESVH16

#define CPUID_FEATURE_RESVH16   BIT48

Reserved.

Definition at line 74 of file CpuId.h.

CPUID_FEATURE_SEGLIM64

#define CPUID_FEATURE_SEGLIM64   BIT43

64-bit segment limit checking

Definition at line 69 of file CpuId.h.

CPUID_FEATURE_SEP

#define CPUID_FEATURE_SEP   BIT11

Fast System Call.

Definition at line 34 of file CpuId.h.

CPUID_FEATURE_SMX

#define CPUID_FEATURE_SMX   BIT38

Safer Mode Extensions (SMX)

Definition at line 64 of file CpuId.h.

CPUID_FEATURE_SS

#define CPUID_FEATURE_SS   BIT27

Self-Snoop.

Definition at line 50 of file CpuId.h.

CPUID_FEATURE_SSE

#define CPUID_FEATURE_SSE   BIT25

Streaming SIMD Extensions.

Definition at line 48 of file CpuId.h.

CPUID_FEATURE_SSE2

#define CPUID_FEATURE_SSE2   BIT26

Streaming SIMD Extensions 2.

Definition at line 49 of file CpuId.h.

CPUID_FEATURE_SSE3

#define CPUID_FEATURE_SSE3   BIT32

Streaming SIMD extensions 3.

Definition at line 58 of file CpuId.h.

CPUID_FEATURE_SSE4_1

#define CPUID_FEATURE_SSE4_1   BIT51

Streaming SIMD Extensions 4.1.

Definition at line 77 of file CpuId.h.

CPUID_FEATURE_SSE4_2

#define CPUID_FEATURE_SSE4_2   BIT52

Streaming SIMD Extensions 4.1.

Definition at line 78 of file CpuId.h.

CPUID_FEATURE_SSSE3

#define CPUID_FEATURE_SSSE3   BIT41

Supplemental SSE3 Instructions.

Definition at line 67 of file CpuId.h.

CPUID_FEATURE_TM

#define CPUID_FEATURE_TM   BIT29

Thermal Monitor (TM1)

Definition at line 52 of file CpuId.h.

CPUID_FEATURE_TM2

#define CPUID_FEATURE_TM2   BIT40

Thermal Monitor 2.

Definition at line 66 of file CpuId.h.

CPUID_FEATURE_TSC

#define CPUID_FEATURE_TSC   BIT4

Time Stamp Counter.

Definition at line 28 of file CpuId.h.

CPUID_FEATURE_TSCTMR

#define CPUID_FEATURE_TSCTMR   BIT56

TSC deadline timer.

Definition at line 82 of file CpuId.h.

CPUID_FEATURE_VME

#define CPUID_FEATURE_VME   BIT1

Virtual Mode Extension.

Definition at line 25 of file CpuId.h.

CPUID_FEATURE_VMM

#define CPUID_FEATURE_VMM   BIT63

VMM (Hypervisor) present.

Definition at line 89 of file CpuId.h.

CPUID_FEATURE_VMX

#define CPUID_FEATURE_VMX   BIT37

Virtual Machine Extensions (VMX)

Definition at line 63 of file CpuId.h.

CPUID_FEATURE_xAPIC

#define CPUID_FEATURE_xAPIC   BIT53

Extended xAPIC Support.

Definition at line 79 of file CpuId.h.

CPUID_FEATURE_XSAVE

#define CPUID_FEATURE_XSAVE   BIT58

XSAVE/XSTOR States.

Definition at line 84 of file CpuId.h.

CPUID_FEATURE_xTPR

#define CPUID_FEATURE_xTPR   BIT46

Task Priority Update Control.

Definition at line 72 of file CpuId.h.

CPUID_L2_CACHE_FEATURE

#define CPUID_L2_CACHE_FEATURE   0x80000006

Definition at line 20 of file CpuId.h.

CPUID_VENDOR_AMD

#define CPUID_VENDOR_AMD   0x68747541

Definition at line 215 of file CpuId.h.

CPUID_VENDOR_INTEL

#define CPUID_VENDOR_INTEL   0x756E6547

Definition at line 214 of file CpuId.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
CpuIdCacheNull	NULL.
CpuIdCacheItlb4K_32_4	Inst TLB: 4K pages, 32 ents, 4-way.
CpuIdCacheItlb4M_2	Inst TLB: 4M pages, 2 ents.
CpuIdCacheDtlb4K_64_4	Data TLB: 4K pages, 64 ents, 4-way.
CpuIdCacheDtlb4M_8_4	Data TLB: 4M pages, 8 ents, 4-way.
CpuIdCacheDtlb4M_32_4	Data TLB: 4M pages, 32 ents, 4-way.
CpuIdCacheL1I_8K	Icache: 8K.
CpuIdCacheL1I_16K	Icache: 16K.
CpuIdCacheL1I_32K	Icache: 32K, 4-way, 64 bytes.
CpuIdCacheL1D_8K	Dcache: 8K.
CpuIdCacheL1D_16K	Dcache: 16K.
CpuIdCacheL1D_16K_4_32	Dcache: 16K, 4-way, 64 byte, ECC.
CpuIdCacheL2_256K_8_64	L2: 256K, 8-way, 64 bytes.
CpuIdCacheL3_512K	L3: 512K.
CpuIdCacheL3_1M	L3: 1M.
CpuIdCacheL3_2M	L3: 2M.
CpuIdCacheL3_4M	L3: 4M.
CpuIdCacheL1D_32K_8	Dcache: 32K, 8-way, 64 byte.
CpuIdCacheL1I_32K_8	Icache: 32K, 8-way.
CpuIdCacheL2_128K_S4	L2: 128K, 4-way, sectored, 64B.
CpuIdCacheL2_192K_S6	L2: 192K, 6-way, sectored, 64B.
CpuIdCacheL2_128K_S2	L2: 128K, 2-way, sectored, 64B.
CpuIdCacheL2_256K_S4	L2: 256K, 4-way, sectored, 64B.
CpuIdCacheL2_384K_S6	L2: 384K, 6-way, sectored, 64B.
CpuIdCacheL2_512K_S4	L2: 512K, 4-way, sectored, 64B.
CpuIdCacheNoCache	No 2nd level or 3rd-level cache.
CpuIdCacheL2_128K	L2: 128K.
CpuIdCacheL2_256K	L2: 256K.
CpuIdCacheL2_512K	L2: 512K.
CpuIdCacheL2_1M_4	L2: 1M, 4-way.
CpuIdCacheL2_2M_4	L2: 2M, 4-way.
CpuIdCacheL3_4M_4_64	L3: 4M, 4-way, 64 bytes.
CpuIdCacheL3_8M_8_64	L3: 8M, 8-way, 64 bytes*‍/.
CpuIdCacheL2_3M_12_64	L3: 3M, 8-way, 64 bytes*‍/.
CpuIdCacheL2_4M_16_64	L2: 4M, 16-way, 64 bytes.
CpuIdCacheL2_6M_12_64	L2: 6M, 12-way, 64 bytes.
CpuIdCacheL2_8M_16_64	L2: 8M, 16-way, 64 bytes.
CpuIdCacheL2_12M_12_64	L2: 12M, 12-way, 64 bytes.
CpuIdCacheL2_16M_16_64	L2: 16M, 16-way, 64 bytes.
CpuIdCacheL2_6M_24_64	L2: 6M, 24-way, 64 bytes.
CpuIdCacheItlb64	Inst TLB: 64 entries.
CpuIdCacheItlb128	Inst TLB: 128 entries.
CpuIdCacheItlb256	Inst TLB: 256 entries.
CpuIdCacheItlb4M2M_7	Inst TLB: 4M/2M, 7 entries.
CpuIdCacheDtlb4M_16_4	Data TLB: 4M, 16 entries, 4-way.
CpuIdCacheDtlb4K_16_4	Data TLB: 4K, 16 entries, 4-way.
CpuIdCacheDtlb4M2M_32_4	Data TLB: 4M/2M, 32 entries.
CpuIdCacheDtlb64	Data TLB: 64 entries.
CpuIdCacheDtlb128	Data TLB: 128 entries.
CpuIdCacheDtlb256	Data TLB: 256 entries.
CpuIdCacheL1D_16K_8_64	Data cache: 16K, 8-way, 64 bytes.
CpuIdCacheL1D_8K_4_64	Data cache: 8K, 4-way, 64 bytes.
CpuIdCacheL1D_16K_4_64	Data cache: 16K, 4-way, 64 bytes.
CpuIdCacheL1D_32K_4_64	Data cache: 32K, 4-way, 64 bytes.
CpuIdCacheTRACE_12K_8	Trace cache 12K-uop, 8-way.
CpuIdCacheTRACE_16K_8	Trace cache 16K-uop, 8-way.
CpuIdCacheTRACE_32K_8	Trace cache 32K-uop, 8-way.
CpuIdCacheTRACE_64K_8	Trace cache 64K-uop, 8-way.
CpuIdCacheL2_1M_4_64	L2: 1M, 4-way, 64 bytes.
CpuIdCacheL2_128K_8_64_2	L2: 128K, 8-way, 64b, 2 lines/sec.
CpuIdCacheL2_256K_8_64_2	L2: 256K, 8-way, 64b, 2 lines/sec.
CpuIdCacheL2_512K_8_64_2	L2: 512K, 8-way, 64b, 2 lines/sec.
CpuIdCacheL2_1M_8_64_2	L2: 1M, 8-way, 64b, 2 lines/sec.
CpuIdCacheL2_2M_8_64	L2: 2M, 8-way, 64 bytes.
CpuIdCacheL2_512K_2_64	L2: 512K, 2-way, 64 bytes.
CpuIdCacheL2_256K_8_32	L2: 256K, 8-way, 32 bytes.
CpuIdCacheL2_512K_8_32	L2: 512K, 8-way, 32 bytes.
CpuIdCacheL2_1M_8_32	L2: 1M, 8-way, 32 bytes.
CpuIdCacheL2_2M_8_32	L2: 2M, 8-way, 32 bytes.
CpuIdCacheL2_512K_4_64	L2: 512K, 4-way, 64 bytes.
CpuIdCacheL2_1M_8_64	L2: 1M, 8-way, 64 bytes.
CpuIdCacheItlb4K_128_4	ITLB: 4KB, 128 entries, 4-way.
CpuIdCacheItlb4M_4_4	ITLB: 4MB, 4 entries, 4-way, or.
CpuIdCacheItlb2M_8_4	ITLB: 2MB, 8 entries, 4-way, or.
CpuIdCacheItlb4M_8	ITLB: 4MB, 8 entries.
CpuIdCacheItlb4K_64_4	ITLB: 4KB, 64 entries, 4-way.
CpuIdCacheDtlb4K_128_4	DTLB: 4KB, 128 entries, 4-way.
CpuIdCacheDtlb4K_256_4	DTLB: 4KB, 256 entries, 4-way.
CpuIdCache2TLB_4K_512_4	2nd-level TLB: 4KB, 512, 4-way
CpuIdCacheL3_512K_4_64	L3: 512KB, 4-way, 64 bytes.
CpuIdCacheL3_1M_4_64	L3: 1M, 4-way, 64 bytes.
CpuIdCacheL3_2M_4_64	L3: 2M, 4-way, 64 bytes.
CpuIdCacheL3_1M_8_64	L3: 1M, 8-way, 64 bytes.
CpuIdCacheL3_2M_8_64	L3: 2M, 8-way, 64 bytes.
CpuIdCacheL3_4M_8_64	L3: 4M, 8-way, 64 bytes.
CpuIdCacheL3_1M5_12_64	L3: 1.5M, 12-way, 64 bytes.
CpuIdCacheL3_3M_12_64	L3: 3M, 12-way, 64 bytes.
CpuIdCacheL3_6M_12_64	L3: 6M, 12-way, 64 bytes.
CpuIdCacheL3_2M_16_64	L3: 2M, 16-way, 64 bytes.
CpuIdCacheL3_4M_16_64	L3: 4M, 16-way, 64 bytes.
CpuIdCacheL3_8M_16_64	L3: 8M, 16-way, 64 bytes.
CpuIdCachePrefetch64	64-Byte Prefetching
CpuIdCachePrefetch128	128-Byte Prefetching

Definition at line 118 of file CpuId.h.