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OpenCore
1.0.4
OpenCore Bootloader
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OpenCore
1.0.4
OpenCore Bootloader
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Go to the source code of this file.
Macros | |
| #define | PCI_BUS_NUMBER_PIIX4 0x00 |
| PIIX4 is on PCI Bus 0. | |
| #define | PCI_DEVICE_NUMBER_PIIX4 7 |
| PIIX4 is Device 7. | |
| #define | PCI_FUNCTION_NUMBER_PIIX4_PMC 3 |
| PMC is Function 3. | |
| #define | PCI_BUS_NUMBER_ICH 0x00 |
| ICH is on PCI Bus 0. | |
| #define | PCI_DEVICE_NUMBER_ICH 31 |
| ICH is Device 31. | |
| #define | PCI_FUNCTION_NUMBER_ICH_LPC 0 |
| LPC is Function 0. | |
| #define | PCI_FUNCTION_NUMBER_ICH_PMC 2 |
| PMC is Function 2. | |
| #define | V_ICH_PCI_VENDOR_ID 0x8086 |
| Intel vendor-id. | |
| #define | V_PIIX4_PMC_PCI_DEVICE_ID 0x7113 |
| Intel PIIX4 PMC device-id. | |
| #define | V_VLV_PMC_PCI_DEVICE_ID 0x0F1C |
| Intel Valley View PMC device-id. | |
| #define | V_CHT_PMC_PCI_DEVICE_ID 0x229C |
| Intel Bay-Trail/Cherry-Trail PMC device-id. | |
| #define | R_PIIX4_PM_BASE 0x40 |
| #define | B_PIIX4_PM_BASE_BAR 0x0000FFC0 |
| #define | R_PIIX4_PMREGMISC 0x80 |
| See PMIOSE. | |
| #define | B_PIIX4_PMREGMISC_PMIOSE 0x1 |
| #define | R_ICH_ACPI_BASE 0x40 |
| #define | B_ICH_ACPI_BASE_BAR 0x0000FF80 |
| #define | R_ICH_ACPI_CNTL 0x44 |
| See ACPI_CNTL. | |
| #define | B_ICH_ACPI_CNTL_ACPI_EN 0x80 |
| #define | R_ICH_BAR2_BASE 0x20 |
| #define | B_ICH_BAR2_BASE_BAR 0x0000FFC0 |
| #define | B_ICH_BAR2_BASE_BAR_EN 0x1 |
| #define | R_ICH_LPC_ACPI_BASE R_ICH_ACPI_BASE |
| #define | B_ICH_LPC_ACPI_BASE_BAR B_ICH_ACPI_BASE_BAR |
| #define | R_ICH_LPC_ACPI_CNTL R_ICH_ACPI_CNTL |
| #define | B_ICH_LPC_ACPI_CNTL_ACPI_EN B_ICH_ACPI_CNTL_ACPI_EN |
| #define | R_ICH_PMC_ACPI_BASE R_ICH_ACPI_BASE |
| #define | B_ICH_PMC_ACPI_BASE_BAR B_ICH_ACPI_BASE_BAR |
| #define | R_ICH_PMC_ACPI_CNTL R_ICH_ACPI_CNTL |
| #define | B_ICH_PMC_ACPI_CNTL_ACPI_EN B_ICH_ACPI_CNTL_ACPI_EN |
| #define | R_ICH_PMC_BAR2_BASE R_ICH_BAR2_BASE |
| #define | B_ICH_PMC_BAR2_BASE_BAR B_ICH_BAR2_BASE_BAR |
| #define | B_ICH_PMC_BAR2_BASE_BAR_EN B_ICH_BAR2_BASE_BAR_EN |
| #define | R_BRSW_PMC_ACPI_BASE 0x40 |
| #define | B_BRSW_PMC_ACPI_BASE_BAR 0xFFFFFE00 |
| #define | R_AMD_ACPI_MMIO_BASE 0xFED80000 |
| AcpiMMioAddr (3-268) | |
| #define | R_AMD_ACPI_MMIO_PMIO_BASE 0x300 |
| PMIO (3-268) | |
| #define | R_AMD_ACPI_PM_TMR_BLOCK 0x64 |
| AcpiPmTmrBlk (3-289) | |
| #define | R_ACPI_PM1_TMR 0x08 |
| #define | V_ACPI_TMR_FREQUENCY 3579545 |
| #define | V_ACPI_PM1_TMR_MAX_VAL 0x01000000 |
| The timer is 24 bit overflow. | |
| #define | PCI_PIIX4_PMC_ADDRESS(Register) |
| Macro to generate the PCI address of any given PIIX4 PMC Register. | |
| #define | PCI_ICH_LPC_ADDRESS(Register) |
| Macro to generate the PCI address of any given ICH LPC Register. | |
| #define | PCI_ICH_PMC_ADDRESS(Register) |
| Macro to generate the PCI address of any given ICH PMC Register. | |
Copyright (C) 2016, The HermitCrabs Lab. All rights reserved.
All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Definition in file GenericIch.h.
| #define B_BRSW_PMC_ACPI_BASE_BAR 0xFFFFFE00 |
Definition at line 83 of file GenericIch.h.
| #define B_ICH_ACPI_BASE_BAR 0x0000FF80 |
Definition at line 52 of file GenericIch.h.
| #define B_ICH_ACPI_CNTL_ACPI_EN 0x80 |
Definition at line 54 of file GenericIch.h.
| #define B_ICH_BAR2_BASE_BAR 0x0000FFC0 |
Definition at line 57 of file GenericIch.h.
| #define B_ICH_BAR2_BASE_BAR_EN 0x1 |
Definition at line 58 of file GenericIch.h.
| #define B_ICH_LPC_ACPI_BASE_BAR B_ICH_ACPI_BASE_BAR |
Definition at line 63 of file GenericIch.h.
| #define B_ICH_LPC_ACPI_CNTL_ACPI_EN B_ICH_ACPI_CNTL_ACPI_EN |
Definition at line 65 of file GenericIch.h.
| #define B_ICH_PMC_ACPI_BASE_BAR B_ICH_ACPI_BASE_BAR |
Definition at line 70 of file GenericIch.h.
| #define B_ICH_PMC_ACPI_CNTL_ACPI_EN B_ICH_ACPI_CNTL_ACPI_EN |
Definition at line 72 of file GenericIch.h.
| #define B_ICH_PMC_BAR2_BASE_BAR B_ICH_BAR2_BASE_BAR |
Definition at line 77 of file GenericIch.h.
| #define B_ICH_PMC_BAR2_BASE_BAR_EN B_ICH_BAR2_BASE_BAR_EN |
Definition at line 78 of file GenericIch.h.
| #define B_PIIX4_PM_BASE_BAR 0x0000FFC0 |
Definition at line 45 of file GenericIch.h.
| #define B_PIIX4_PMREGMISC_PMIOSE 0x1 |
Definition at line 47 of file GenericIch.h.
| #define PCI_BUS_NUMBER_ICH 0x00 |
ICH is on PCI Bus 0.
Definition at line 32 of file GenericIch.h.
| #define PCI_BUS_NUMBER_PIIX4 0x00 |
PIIX4 is on PCI Bus 0.
Definition at line 26 of file GenericIch.h.
| #define PCI_DEVICE_NUMBER_ICH 31 |
ICH is Device 31.
Definition at line 33 of file GenericIch.h.
| #define PCI_DEVICE_NUMBER_PIIX4 7 |
PIIX4 is Device 7.
Definition at line 27 of file GenericIch.h.
| #define PCI_FUNCTION_NUMBER_ICH_LPC 0 |
LPC is Function 0.
Definition at line 34 of file GenericIch.h.
| #define PCI_FUNCTION_NUMBER_ICH_PMC 2 |
PMC is Function 2.
Definition at line 35 of file GenericIch.h.
| #define PCI_FUNCTION_NUMBER_PIIX4_PMC 3 |
PMC is Function 3.
Definition at line 28 of file GenericIch.h.
| #define PCI_ICH_LPC_ADDRESS | ( | Register | ) |
Macro to generate the PCI address of any given ICH LPC Register.
Definition at line 102 of file GenericIch.h.
| #define PCI_ICH_PMC_ADDRESS | ( | Register | ) |
Macro to generate the PCI address of any given ICH PMC Register.
Definition at line 106 of file GenericIch.h.
| #define PCI_PIIX4_PMC_ADDRESS | ( | Register | ) |
Macro to generate the PCI address of any given PIIX4 PMC Register.
Definition at line 98 of file GenericIch.h.
| #define R_ACPI_PM1_TMR 0x08 |
Definition at line 93 of file GenericIch.h.
| #define R_AMD_ACPI_MMIO_BASE 0xFED80000 |
AcpiMMioAddr (3-268)
Definition at line 87 of file GenericIch.h.
| #define R_AMD_ACPI_MMIO_PMIO_BASE 0x300 |
PMIO (3-268)
Definition at line 88 of file GenericIch.h.
| #define R_AMD_ACPI_PM_TMR_BLOCK 0x64 |
AcpiPmTmrBlk (3-289)
Definition at line 89 of file GenericIch.h.
| #define R_BRSW_PMC_ACPI_BASE 0x40 |
Definition at line 82 of file GenericIch.h.
| #define R_ICH_ACPI_BASE 0x40 |
Definition at line 51 of file GenericIch.h.
| #define R_ICH_ACPI_CNTL 0x44 |
See ACPI_CNTL.
Definition at line 53 of file GenericIch.h.
| #define R_ICH_BAR2_BASE 0x20 |
Definition at line 56 of file GenericIch.h.
| #define R_ICH_LPC_ACPI_BASE R_ICH_ACPI_BASE |
Definition at line 62 of file GenericIch.h.
| #define R_ICH_LPC_ACPI_CNTL R_ICH_ACPI_CNTL |
Definition at line 64 of file GenericIch.h.
| #define R_ICH_PMC_ACPI_BASE R_ICH_ACPI_BASE |
Definition at line 69 of file GenericIch.h.
| #define R_ICH_PMC_ACPI_CNTL R_ICH_ACPI_CNTL |
Definition at line 71 of file GenericIch.h.
| #define R_ICH_PMC_BAR2_BASE R_ICH_BAR2_BASE |
Definition at line 76 of file GenericIch.h.
| #define R_PIIX4_PM_BASE 0x40 |
Definition at line 44 of file GenericIch.h.
| #define R_PIIX4_PMREGMISC 0x80 |
See PMIOSE.
Definition at line 46 of file GenericIch.h.
| #define V_ACPI_PM1_TMR_MAX_VAL 0x01000000 |
The timer is 24 bit overflow.
Definition at line 95 of file GenericIch.h.
| #define V_ACPI_TMR_FREQUENCY 3579545 |
Definition at line 94 of file GenericIch.h.
| #define V_CHT_PMC_PCI_DEVICE_ID 0x229C |
Intel Bay-Trail/Cherry-Trail PMC device-id.
Definition at line 40 of file GenericIch.h.
| #define V_ICH_PCI_VENDOR_ID 0x8086 |
Intel vendor-id.
Definition at line 37 of file GenericIch.h.
| #define V_PIIX4_PMC_PCI_DEVICE_ID 0x7113 |
Intel PIIX4 PMC device-id.
Definition at line 38 of file GenericIch.h.
| #define V_VLV_PMC_PCI_DEVICE_ID 0x0F1C |
Intel Valley View PMC device-id.
Definition at line 39 of file GenericIch.h.
1.12.0