OpenCore  1.0.4
OpenCore Bootloader
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ActivateHpetSupport.c
Go to the documentation of this file.
1
15#include <Uefi.h>
16
17#include <IndustryStandard/Pci.h>
18
19#include <Protocol/PciIo.h>
20
21#include <Library/BaseMemoryLib.h>
22#include <Library/DebugLib.h>
23#include <Library/IoLib.h>
24#include <Library/UefiBootServicesTableLib.h>
26
27#include "PciExtInternal.h"
28
29VOID
31 VOID
32 )
33{
34 EFI_STATUS Status;
35 UINTN HandleCount;
36 EFI_HANDLE *HandleBuffer;
37 UINTN Index;
38 EFI_PCI_IO_PROTOCOL *PciIo;
39 PCI_CLASSCODE ClassCode;
40 UINT32 Rcba;
41 UINT32 Hptc;
42
43 Status = gBS->LocateHandleBuffer (
44 ByProtocol,
45 &gEfiPciIoProtocolGuid,
46 NULL,
47 &HandleCount,
48 &HandleBuffer
49 );
50
51 if (EFI_ERROR (Status)) {
52 DEBUG ((DEBUG_INFO, "OCDM: No PCI devices for HPET support - %r\n", Status));
53 return;
54 }
55
56 for (Index = 0; Index < HandleCount; ++Index) {
57 Status = gBS->HandleProtocol (
58 HandleBuffer[Index],
59 &gEfiPciIoProtocolGuid,
60 (VOID **)&PciIo
61 );
62
63 if (EFI_ERROR (Status)) {
64 continue;
65 }
66
67 Status = PciIo->Pci.Read (
68 PciIo,
69 EfiPciIoWidthUint8,
70 PCI_CLASSCODE_OFFSET,
71 sizeof (PCI_CLASSCODE) / sizeof (UINT8),
72 &ClassCode
73 );
74 if (EFI_ERROR (Status)) {
75 continue;
76 }
77
78 if ((ClassCode.BaseCode == PCI_CLASS_BRIDGE) && (ClassCode.SubClassCode == PCI_CLASS_BRIDGE_ISA)) {
79 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, PCI_BRIDGE_RCBA_OFFSET, 1, &Rcba);
80 if (EFI_ERROR (Status)) {
81 continue;
82 }
83
84 DEBUG ((
85 DEBUG_INFO,
86 "OCDM: Discovered RCBA device at %u/%u at 0x%X\n",
87 (UINT32)(Index + 1),
88 (UINT32)HandleCount,
89 Rcba
90 ));
91
92 //
93 // Disabled completely. Ignore.
94 //
95 if ((Rcba & PCI_BRIDGE_RCBA_ADDRESS_MASK) == 0) {
96 continue;
97 }
98
99 //
100 // Disabled access. Try to enable.
101 //
102 if ((Rcba & PCI_BRIDGE_RCBA_ACCESS_ENABLE) == 0) {
104 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, PCI_BRIDGE_RCBA_OFFSET, 1, &Rcba);
105 }
106
108
109 Hptc = MmioRead32 (Rcba + RCBA_HTPC_REGISTER);
110
111 DEBUG ((
112 DEBUG_INFO,
113 "OCDM: Discovered HPTC register with 0x%X value\n",
114 Hptc
115 ));
116
117 if ((Hptc & RCBA_HTPC_HPET_ENABLE) == 0) {
119 Hptc = MmioRead32 (Rcba + RCBA_HTPC_REGISTER);
120
121 DEBUG ((
122 DEBUG_INFO,
123 "OCDM: Updated HPTC register with HPET has 0x%X value\n",
124 Hptc
125 ));
126 }
127 }
128 }
129}
VOID ActivateHpetSupport(VOID)
EFI_BOOT_SERVICES * gBS
#define RCBA_HTPC_REGISTER
#define PCI_BRIDGE_RCBA_OFFSET
#define PCI_BRIDGE_RCBA_ADDRESS_MASK
#define RCBA_HTPC_HPET_ENABLE
#define PCI_BRIDGE_RCBA_ACCESS_ENABLE
UINT32 EFIAPI MmioRead32(IN UINTN Address)
Definition UserMisc.c:623
UINT32 EFIAPI MmioWrite32(IN UINTN Address, IN UINT32 Value)
Definition UserMisc.c:651