OpenCore  1.0.4
OpenCore Bootloader
Loading...
Searching...
No Matches
Macros
PciExtInternal.h File Reference

Go to the source code of this file.

Macros

#define PCI_BRIDGE_RCBA_OFFSET   0xF0U
 
#define PCI_BRIDGE_RCBA_ADDRESS_MASK   0xFFFFC000U
 
#define PCI_BRIDGE_RCBA_ACCESS_ENABLE   BIT0
 
#define RCBA_HTPC_REGISTER   0x3404U
 
#define RCBA_HTPC_HPET_ENABLE   BIT7
 
#define XHC_HCCPARAMS_OFFSET   0x10
 
#define XHC_NEXT_CAPABILITY_MASK   0xFF00
 
#define XHC_CAPABILITY_ID_MASK   0xFF
 
#define XHC_USBCMD_OFFSET   0x0
 USB Command Register Offset.
 
#define XHC_USBSTS_OFFSET   0x4
 USB Status Register Offset.
 
#define XHC_POLL_DELAY   1000
 
#define EHC_BAR_INDEX   0x0
 
#define EHC_HCCPARAMS_OFFSET   0x8
 
#define EHC_USBCMD_OFFSET   0x0
 USB Command Register Offset.
 
#define EHC_USBSTS_OFFSET   0x4
 USB Status Register Offset.
 
#define EHC_USBINT_OFFSET   0x8
 USB Interrupt Enable Register.
 
#define PCI_CLASS_MEDIA_HDA   0x03
 
#define PCI_MEDIA_TCSEL_OFFSET   0x44U
 
#define TCSEL_CLASS_MASK   0x7U
 
#define PCI_BAR_CAP_1MB   BIT0
 
#define PCI_BAR_CAP_2MB   BIT1
 
#define PCI_BAR_CAP_4MB   BIT2
 
#define PCI_BAR_CAP_8MB   BIT3
 
#define PCI_BAR_CAP_16MB   BIT4
 
#define PCI_BAR_CAP_32MB   BIT5
 
#define PCI_BAR_CAP_64MB   BIT6
 
#define PCI_BAR_CAP_128MB   BIT7
 
#define PCI_BAR_CAP_256MB   BIT8
 
#define PCI_BAR_CAP_512MB   BIT9
 
#define PCI_BAR_CAP_1GB   BIT10
 
#define PCI_BAR_CAP_2GB   BIT11
 
#define PCI_BAR_CAP_4GB   BIT12
 
#define PCI_BAR_CAP_8GB   BIT13
 
#define PCI_BAR_CAP_16GB   BIT14
 
#define PCI_BAR_CAP_32GB   BIT15
 
#define PCI_BAR_CAP_64GB   BIT16
 
#define PCI_BAR_CAP_128GB   BIT17
 
#define PCI_BAR_CAP_256GB   BIT18
 
#define PCI_BAR_CAP_512GB   BIT19
 
#define PCI_BAR_CAP_LIMIT(BarSize)
 

Detailed Description

Copyright (C) 2021, vit9696. All rights reserved.

All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file PciExtInternal.h.

Macro Definition Documentation

◆ EHC_BAR_INDEX

#define EHC_BAR_INDEX   0x0

EHCI registers.

Definition at line 56 of file PciExtInternal.h.

◆ EHC_HCCPARAMS_OFFSET

#define EHC_HCCPARAMS_OFFSET   0x8

Definition at line 57 of file PciExtInternal.h.

◆ EHC_USBCMD_OFFSET

#define EHC_USBCMD_OFFSET   0x0

USB Command Register Offset.

Definition at line 58 of file PciExtInternal.h.

◆ EHC_USBINT_OFFSET

#define EHC_USBINT_OFFSET   0x8

USB Interrupt Enable Register.

Definition at line 60 of file PciExtInternal.h.

◆ EHC_USBSTS_OFFSET

#define EHC_USBSTS_OFFSET   0x4

USB Status Register Offset.

Definition at line 59 of file PciExtInternal.h.

◆ PCI_BAR_CAP_128GB

#define PCI_BAR_CAP_128GB   BIT17

Definition at line 101 of file PciExtInternal.h.

◆ PCI_BAR_CAP_128MB

#define PCI_BAR_CAP_128MB   BIT7

Definition at line 91 of file PciExtInternal.h.

◆ PCI_BAR_CAP_16GB

#define PCI_BAR_CAP_16GB   BIT14

Definition at line 98 of file PciExtInternal.h.

◆ PCI_BAR_CAP_16MB

#define PCI_BAR_CAP_16MB   BIT4

Definition at line 88 of file PciExtInternal.h.

◆ PCI_BAR_CAP_1GB

#define PCI_BAR_CAP_1GB   BIT10

Definition at line 94 of file PciExtInternal.h.

◆ PCI_BAR_CAP_1MB

#define PCI_BAR_CAP_1MB   BIT0

When the bit of Capabilities Set, it indicates that the Function supports operating with the BAR sized to (2^Bit) MB. Example:

  • Bit 0 is set: supports operating with the BAR sized to 1 MB
  • Bit 1 is set: supports operating with the BAR sized to 2 MB
  • Bit n is set: supports operating with the BAR sized to (2^n) MB

Definition at line 84 of file PciExtInternal.h.

◆ PCI_BAR_CAP_256GB

#define PCI_BAR_CAP_256GB   BIT18

Definition at line 102 of file PciExtInternal.h.

◆ PCI_BAR_CAP_256MB

#define PCI_BAR_CAP_256MB   BIT8

Definition at line 92 of file PciExtInternal.h.

◆ PCI_BAR_CAP_2GB

#define PCI_BAR_CAP_2GB   BIT11

Definition at line 95 of file PciExtInternal.h.

◆ PCI_BAR_CAP_2MB

#define PCI_BAR_CAP_2MB   BIT1

Definition at line 85 of file PciExtInternal.h.

◆ PCI_BAR_CAP_32GB

#define PCI_BAR_CAP_32GB   BIT15

Definition at line 99 of file PciExtInternal.h.

◆ PCI_BAR_CAP_32MB

#define PCI_BAR_CAP_32MB   BIT5

Definition at line 89 of file PciExtInternal.h.

◆ PCI_BAR_CAP_4GB

#define PCI_BAR_CAP_4GB   BIT12

Definition at line 96 of file PciExtInternal.h.

◆ PCI_BAR_CAP_4MB

#define PCI_BAR_CAP_4MB   BIT2

Definition at line 86 of file PciExtInternal.h.

◆ PCI_BAR_CAP_512GB

#define PCI_BAR_CAP_512GB   BIT19

Definition at line 103 of file PciExtInternal.h.

◆ PCI_BAR_CAP_512MB

#define PCI_BAR_CAP_512MB   BIT9

Definition at line 93 of file PciExtInternal.h.

◆ PCI_BAR_CAP_64GB

#define PCI_BAR_CAP_64GB   BIT16

Definition at line 100 of file PciExtInternal.h.

◆ PCI_BAR_CAP_64MB

#define PCI_BAR_CAP_64MB   BIT6

Definition at line 90 of file PciExtInternal.h.

◆ PCI_BAR_CAP_8GB

#define PCI_BAR_CAP_8GB   BIT13

Definition at line 97 of file PciExtInternal.h.

◆ PCI_BAR_CAP_8MB

#define PCI_BAR_CAP_8MB   BIT3

Definition at line 87 of file PciExtInternal.h.

◆ PCI_BAR_CAP_LIMIT

#define PCI_BAR_CAP_LIMIT ( BarSize)
Value:
((1U << ((BarSize) + 1)) - 1)

Capability limit mask from BarSize (e.g. PciBar1MB).

Definition at line 108 of file PciExtInternal.h.

◆ PCI_BRIDGE_RCBA_ACCESS_ENABLE

#define PCI_BRIDGE_RCBA_ACCESS_ENABLE   BIT0

Access bit of the Root Complex Base Address register.

Definition at line 31 of file PciExtInternal.h.

◆ PCI_BRIDGE_RCBA_ADDRESS_MASK

#define PCI_BRIDGE_RCBA_ADDRESS_MASK   0xFFFFC000U

Address bits of the Root Complex Base Address register.

Definition at line 26 of file PciExtInternal.h.

◆ PCI_BRIDGE_RCBA_OFFSET

#define PCI_BRIDGE_RCBA_OFFSET   0xF0U

Offset to Root Complex Base Address for a PCI bridge device.

Definition at line 21 of file PciExtInternal.h.

◆ PCI_CLASS_MEDIA_HDA

#define PCI_CLASS_MEDIA_HDA   0x03

HDA audio class missing from Pci22.h.

Definition at line 65 of file PciExtInternal.h.

◆ PCI_MEDIA_TCSEL_OFFSET

#define PCI_MEDIA_TCSEL_OFFSET   0x44U

Offset to TCSEL register for a PCI media device.

Definition at line 70 of file PciExtInternal.h.

◆ RCBA_HTPC_HPET_ENABLE

#define RCBA_HTPC_HPET_ENABLE   BIT7

HPET enable bit in HTPC.

Definition at line 41 of file PciExtInternal.h.

◆ RCBA_HTPC_REGISTER

#define RCBA_HTPC_REGISTER   0x3404U

HTPC register in RCBA.

Definition at line 36 of file PciExtInternal.h.

◆ TCSEL_CLASS_MASK

#define TCSEL_CLASS_MASK   0x7U

TCSEL class mask.

Definition at line 75 of file PciExtInternal.h.

◆ XHC_CAPABILITY_ID_MASK

#define XHC_CAPABILITY_ID_MASK   0xFF

Definition at line 48 of file PciExtInternal.h.

◆ XHC_HCCPARAMS_OFFSET

#define XHC_HCCPARAMS_OFFSET   0x10

XHCI registers.

Definition at line 46 of file PciExtInternal.h.

◆ XHC_NEXT_CAPABILITY_MASK

#define XHC_NEXT_CAPABILITY_MASK   0xFF00

Definition at line 47 of file PciExtInternal.h.

◆ XHC_POLL_DELAY

#define XHC_POLL_DELAY   1000

Definition at line 51 of file PciExtInternal.h.

◆ XHC_USBCMD_OFFSET

#define XHC_USBCMD_OFFSET   0x0

USB Command Register Offset.

Definition at line 49 of file PciExtInternal.h.

◆ XHC_USBSTS_OFFSET

#define XHC_USBSTS_OFFSET   0x4

USB Status Register Offset.

Definition at line 50 of file PciExtInternal.h.